Modeling of OFDM Based Transceiver for Broadband Powerline Communication

In the recent past power line communication has emerged as an attractive choice for high speed data transfer and is looked upon as inexpensive and reliable media suitable for broadband inter-net access, home and office automation, in-vehicle data communication etc. In this paper we pre-sent an architecture for the physical layer of a PLC transceiver based on Orthogonal Frequency Division Multiplexing (OFDM) and the impact on multipath distortion for PLC transmission in terms of bit error rate. Since there is no standard PLC channel model available, a widely accepted multipath channel model is used for simulation purpose. Simulation results as well as FPGA synthesis verify the effectiveness of the proposed architecture for PLC modem design at 110 Mbps data rate.


Introduction
In the last decade power line communication (PLC) has become very popular for broadband access, multimedia sharing and the main advantage is that they exploit the existing power line network [1]. On the other hand, power lines constitute a challenging communication medium in terms of noise, attenuation and multipath propagation [2]. The noise traversing power lines can be characterized as a combination of coloured background noise, narrowband noise and impulsive noise. The frequency dependent attenuation characteristics of power lines and multipath stemming from impedance mismatches are the other factors which have to be dealt with in order to establish a reliable high-speed PLC system. Considering power line noise and attenuation, the frequency zone between 1 -30 MHz is believed to be ideal for the operation of PLC systems [3] [4]. This frequency range is also used by Amateur radio operators, international short wave broadcasters and a variety of communication systems, thus a potential for harmful interference with other user exists [5]. Orthogonal Frequency Division Multiplexing (OFDM) is considered as the most favourable modulation scheme for a severe communication environment such as the PLC channel [6]. Comparing to single carrier modulation scheme OFDM segments the available bandwidth into a large number of closely-spaced orthogonal subcarriers, each occupying a much narrower bandwidth. In this way, OFDM can combat frequency selective attenuation and multipath propagation effect. This paper presents the design of the physical layer of a PLC transceiver based on the OFDM modulation scheme and the impact of multipath distortion on PLC transmission in terms of bit error rate (BER). For the completeness of the study, Zimmermann and Dostert's well-known PLC channel model is taken into consideration [7]. The designed system is fully described using VHDL and synthesized on a Xilinx Spartan 6 FPGA device [8]. Every OFDM system consists of a pair of a transmitter and a receiver circuit, which are implemented digitally on two different FPGA chips. The tested OFDM systems differ on the adopted modulation technique and the number of subcarriers used. The choice to develop the communication systems on FPGA chips provides a low-cost, easy to implement, digital solution, and the fact that FPGAs are reprogrammable devices makes possible the reuse of the same FPGA chips for the different OFDM systems. All OFDM systems occupy the frequency zone 1 -30 MHz.

System Design
In OFDM, the parallel data streams are first mapped into BPSK data which then modulate a number of subcarriers using discrete Fourier transform (DFT) producing an OFDM signal. An OFDM symbol starting at t = t s , carrying a sequence d i of BPSK symbols in N subcarriers can be expressed by the following complex baseband representation [9]: where T is the symbol duration. Figure 1 shows the basic operation of OFDM. An important task in the design of OFDM systems is the choice of the different parameters and the tradeoffs between them. Three requirements are of major importance: bandwidth, bit rate and delay spread [9]. According to Nee et al. [9], a good length of the CP should be around two to four times the root-mean-squared delay spread. The longer the symbol duration relative to the CP length, lesser is the loss in SNR, due to the CP. At the same time, this means a bigger number of subcarriers with less spacing given a specific bandwidth, adding extra implementation complexity and leading to problems related to frequency and phase offset. OFDM offers a great spectral efficiency which is necessary for broadband communications through a channel with very limited spectral resources like the power line channel. The long symbol period in OFDM gives the technique extra strength against multipath propagation and ISI. Although the insertion of a cyclic prefix reduces the useful data rate of the system, it gets rid of any ISI or ICI that can result from multipath when designed to have a longer duration than the delay spread of the PLC channel. The core element of OFDM is the IDFT/DFT process. This can be implemented in practice using the FFT algorithm in a very efficient and cost-effective way. The power line network is a hostile channel when considering broadband high-speed communications. One of the most crucial properties of this channel affecting high-speed communications is the presence of random time-varying impulsive noise. OFDM performs better than single-carrier modulation techniques in the presence of impulsive noise [10] [11]. In the receiver part of OFDM, the received signal including impulsive noise is divided by the number of subcarriers through the DFT operation, which results in a significant reduction of the effect of impulsive noise.
A general block diagram of the proposed PLC transceiver is shown in Figure 2. At the transmitter side, the information bits first undergo channel coding and interleaving before mapping into BPSK symbols. Pilots are inserted in the data to detect the channel transfer characteristics. Then the data stream is then converted to a parallel stream that is modulated by means of a 4096-point IFFT block. Each OFDM symbol generated by this block is composed of 1974 data subcarriers and 74 guard subcarriers. The modulated data is converted back to a serial stream and a cyclic prefix (CP) of 1252 samples is inserted at the beginning of the symbol, in order to avoid inter symbol interference (ISI) in the case of any delay at the receiver. At the receiver side, more or less the opposite happens in addition to the required synchronization and channel equalization using the information delivered by the pilot symbols.
For the PLC channel model a widely accepted multipath channel model introduced by Zimmermann and Dostert [7] is used for simulation purpose.The model is based on practical measurements of actual power line networks and is given by the channel transfer function: where N p is the number of multipaths, g i and d i are the weighting factor and length of the i th path respectively. Frequency-dependant attenuation is modeled by the parameters a 0 , a 1 and k. In the model, the first exponential presents attenuation in the PLC channel, whereas the second exponential, with the propagation speed v p , describes the echo scenario. The attenuation parameters for a 4-path model and a 15-path model were obtained using physical measurements in [2] and are summarized in Table 1 and Table 2 respectively. During simulation the periodic synchronous Impulsive noise and AWGN are employed simultaneously on the power line channel and they have different impacts upon the communication performance.

Synthesis and Simulation Results
In order to evaluate the bit error rate (BER) performance of the designed transceiver over power line noise, the receiver response is simulated using MATLAB R2013a and the resulting BER plot is shown in Figure 3. On the basis of b o E N it is clear that 15 path BPSK requires more energy per bit than 4 path BPSK model. But it results into the higher data for a system. The total designed system was described using hardware descriptive language and synthesized on the Xilinx Spartan 6 FPGA device using the Xilinx ISE 14.4 software.

Conclusion
We have presented an architecture for the physical layer of a PLC transceiver based on OFDM and the system synthesized on a Xilinx Spartan 6 FPGA device, supports data rate up to 110 Mbps. The modulation scheme and