A Domain Extension Algorithm for Digital Error Correction of Pipeline ADCs

A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise ratio (SNR) and the minor analog and digital circuit modifications. Behavioral simulation results are presented to demonstrate the effectiveness of the algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and 30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for a 10-bit pipeline ADC.


Introduction
ADCs are widely used in many areas, such as music recording, healthcare, radar systems and communication [1].A trend of the modern ADC design is the use of digital background calibration to compensate for the raw performance of analog circuits [2][3][4][5][6][7][8][9].However, many digital background calibrations can only correct gain errors [10,11], which are caused by finite op-amp gain and capacitor mismatches.This leaves the comparator offsets corrected by the traditional digital error correction technique or not corrected at all.The traditional 1.5bit/stage ADC can only correct the comparator offsets within ± ref 4  V [12].For small-geometry transistors, typical mismatches in the width, length and threshold voltage can lead to significant comparator offsets [13].
Comparator offsets greatly limit the accuracy of a switched capacitor pipeline ADC.In this paper, a new algorithm is developed to improve the comparator offset correction ability for the 1.5-bit/stage pipeline ADC.This innovative algorithm increases the comparator offset toleration ability by 50%.In addition, the algorithm also provides crucial information on both overflow and underflow situations.

Domain Extension Algorithm
The residue plot of a real ADC with comparator offsets is shown using dashed lines.In this case, the maximum comparator offset is ref 4  V and the corresponding maximum output equals to ref V .Since the output of the current stage is the input of the next stage, and the input range is from ref V , the out of range output leads to code loss.In order to prevent the ADC from code loss, the comparator offsets should be within the range of with an added overflow/underflow judgment.Two Matlab behavioral simulations are used to illustrate the improvement of the comparator offset correction ability for the proposed ADC.The first ADC behavioral simulation includes eight traditional 1.5-bit/stage converters followed by a flash ADC, and the second ADC behavioral simulation includes eight trial 1.5-bit/stage converters also followed by a flash ADC.In these simulations, the absolute values of the comparator offsets are set between 0 and ref 0.5V .In order to control and narrow research findings, all 1.5-bit/stage ADCs are onlycomplicated by the comparator offsets.In addition, the flash ADCs setting are ideal.In these simulations, the total number of conversions is 14  2 .The total miscode numbers, and their related comparator offsets, are show in , for the ADC based on the proposed algorithm.
The transfer function of the traditional 1.5-bit/stage pipeline ADC is given by the following equation [14]: . ( The transfer function of the proposed five-domain 1.5bit/stage pipeline ADC is given by the following equation: This proposed ADC consists of eight 1.5-bit stages followed by a 2-bit flash ADC.There are 12 total output bits, 10usable bits and the first two bits are utilized as overflow/underflow bits.Figure 3 shows the algorithm process.In order to have the digital output of five-domain 1.5-bit/stage ADC consistent with the traditional 1.5-bit/stage ADC, the subtraction of one operation is needed.Since 000 minus 1 is negative, adding a "1" in front of the digital output of the first stage avoids the negative number.For the same reason, the later stages also need to subtract one operation.In addition, the dislocation addition should be implemented before the subtraction of one.The first two bits are overflow/underflow bits.Therefore, when they are "11" or "01", they will reference to the input signal beyond or below the reference  The circuit level implementation of Equation ( 2) is given by , 000 , 001 , 010 , 011 , 100 In Equation ( 3), the two capacitors are equal.When the required gain is one, the circuit level realization is the same as the traditional technique, and capacitor 2 C connects to the corresponding reference voltage.However, a gain of two for ref V cannot be realized through the traditional technique since one of the capacitors is the feedback capacitor.The maximum gain for ref V is the non-feedback capacitor divided by the feedback capacitor, which is one.To extend the domain, a new method is proposed.In this new method V dd need to be set to twice the ref V .The first and the last equations of (3) are Φ is high, the converters work on the sample phase, input is sampled on the two capacitors simultaneously.When 2 Φ is high, they work on the amplification phase, the feedback capacitor 1 C connects to the output and the non-feedback capacitor 2 C connects to the corresponding reference voltage.
The proposed algorithm slightly modifies the analog.Two comparators are added to extend the quantify domains, and two references are used to provide a gain of two for ref V .Since the actual configuration is fully dif-

Simulation Results
In order to demonstrate the effectiveness of the domain extension algorithm, a 10-bit pipeline ADC was simulated in MATLAB.The ADC consisted of eight fivedomain 1.5-bit/stage converters and a 2-bit flash ADC.In the simulation, all absolute values of comparator offsets were set to

Conclusion
The decrease of the transistor geometry causes problematic mismatches in width, length and threshold voltage, which leads to significant comparator offsets.These comparator offsets, in turn, greatly limit the performance of ADCs.However, the traditional digital error correction technique can only correct the absolute value of comparator offsets lower than ref 4 V .Therefore, in order to improve the comparator offset toleration ability, a domain extension algorithm has been presented, which can correct the absolute value of comparator offsets within ref 3 8 . This new approach involves minor analog and digital modifications and increases the comparator offset toleration ability by 50% with overflow/underflow judgment.Simulation results have revealed significant improvements of SFDR, THD and SNR performance.

Figure 1 (V − and ref 4 V
Figure 1(a) shows the residue plot of the traditional 1.5bit/stage ADC.In Figure 1(a), two ideal threshold voltages are ref 4 V − and ref 4 V shown with dotted lines.The coded range is from ref

Figure 1 (Figure 1 .
Figure 1.(a) Residue plot of the traditional 1.5-bit/stage ADC and (b) residue plot of the five-domain 1.5-bit/stage ADC.range is from

Figure 2 .
According to Figure 2, for the ADC based on the traditional digital error correction technique, miscodes occur when the absolute values of the comparator offsets are higher than ref 4 V .By comparison, no miscodes occur for the absolute values of the comparator offsets lower than ref 3 8 V

Figure 4 (.
c) shows the processing of output codes based on the traditional digital error correction technique with the comparator offsets the same as Figure 4(a), but the threshold voltages are Figure 4(d) shows the processing of output based on the traditional technique with the comparator offsets set to be zero.These three cases, Figures 4(a), 4(b), and 4(d), have the correct digital output, while Figure 4(c) is different from the other three because the traditional technique cannot correct the absolute values of comparator offsets higher than |V ref /4|.

)Figures 5
Figures 5(a) and 5(b) are the circuit configurations based on the traditional technique and the proposed algorithm, respectively.ref V is simplified by r V in the figures.Although the actual configurations are fully differential, the sing-ended the configurations are shown for simplicity.When 1Φ is high, the converters work on the sample phase, input is sampled on the two capacitors simultaneously.When 2 Φ is high, they work on the amplification phase, the feedback capacitor 1 C connects to the output and the non-feedback capacitor 2 C connects to the corresponding reference voltage.The proposed algorithm slightly modifies the analog.Two comparators are added to extend the quantify domains, and two references are used to provide a gain of two for ref V .Since the actual configuration is fully dif-

Figure 4 .Figure 5 .
Figure 4. (a) Example of the proposed algorithm with the comparator offset of 3V ref /8; (b) Example of the proposed algorithm with no comparator offset; (c) Example of the traditional algorithm with the comparator offset of 3V ref /8; (d) Example of the traditional algorithm with no comparator offset.
was set to 45-MHz, and sample rate was set to 100-MS/s.The Fast Fourier Transform (FFT) plot of this simulation using the traditional method is shown in Figure6(a).The dynamic performance as shown in the FFT plot is recorded as 34.62-dBSFDR, 34.63-dB THD, and 30.33-dBSNR.

Figure 6 ( 7 . 8 VFigure 6 .
Figure 6.FFT plots of a 10-bit pipeline ADC using (a) the traditional digital error correction technique and (b) the proposed algorithm.

Figure 7 .
Figure 7. Simulated dynamic performance using (a) the traditional digital error correction technique and (b) the proposed algorithm.