A Quadrature Oscillator Based on a New “ Optimized DDCC ” All-Pass Filter

In this paper, a new voltage-mode (VM), all-pass filter utilizing two second-generation current conveyors and tow differential difference current conveyors (DDCCs) is proposed. This filter uses a number of passive elements grounded capacitor. This structure of filter is used to realize a quadrature oscillator. The proposed circuits employ tow optimized differential difference translinear second generation current conveyers (DDCCII). These structures are simulated using the spice simulation in the ADS software and CMOS 0.18 μm process of TSMC technology to confirm the theory. The pole frequency can be tuned in the range of [11.6 39.6 MHz] by a simple variation of a DC current.


Introduction
Differential difference current conveyors (DDCCs) are useful current-mode building blocks and many authors have demonstrated their versatility in CMOS analog circuit esign [1].Generalized impedance converter, filter, oscillator, quadrature oscillator, floating or grounding resistor and inductance simulation are an important domain of application of DDCCs [2][3][4].Indeed, the realizetion of voltage-mode (VM) first-order all-pass filters is quite recent [5].These structures present some advantages, such as the possibility to control the frequency or the gain after integration [6][7][8].DDCC-based filter or quadrature oscillator presents a good solution to avoid limitations of Surface Acoustic Wave, such as problems of integration, impedance matching, tuning, linearity, etc [3,6].
In order to get tuning parameters for the proposed structure, translinear differential difference second generation current controlled conveyor based structure seems to be the most attractive [9][10][11].This DDCC gives a possibility to control the functions [5][6][7][8] characteristics by parasitic resistor at port X by means of a current source [12][13][14].These DDCCs are extended in CMOS technology to realize a high frequency application such as filters, oscillators, quadrature oscillator and buffer [10,15,16].To minimize the problem given by the passive element, floating and grounding resistor or floating and grounding capacitor or floating and grounding inductor, DDCC seems to be the most attractive [3,4,14].
This paper is organized as follows: In Section II, we present the proposed all-pass filter which uses two second generation current conveyor and two optimized differential difference current conveyors (DDCCs) and one grounded capacitor.This structure is ameliorated by replacing the grounding capacitor by CMOS Varactors.In Section III, we give the optimized DDCC implementation CMOS 0.18 μm process of TSMC technology.After this, we illustrate the simulation results of the optimized differential difference translinear second generation current conveyors (DDCCs) implemented in 0.18 μm CMOS technology.In Section IV, we illustrate the simulation results of the proposed DDCC all pass filter.In Section V, we present the CCII-based Quadrature oscillator architecture.This application using the proposed filter connected to an integrator in a closed loop.Finally, to validate theoretical analysis, the different circuits are designed and simulated using spice simulation in the ADS software.

The Proposed All-Pass Filter
A number of current and voltage mode all-pass filters employing the DDCC have been suggested [17].However most of these realizations employ floating capacitors and resistors which require a large area to be implemented by MOS transistors.The proposed structure use two DDCC, two CCII and only grounded capacitor.The input of the voltage-mode (VM) all-pass filter is connected to the Y terminal (high input impedance) and its output is connected to the X terminal (low output impedance).For this reason the proposed structure doesn't necessitate a buffer cascade with another bloc.The architecture of the filter is given in Figure 1.
The transfer function and the phase of this filter can be expressed by: The pole frequency of the filter is calculated as: The type of the filter gives a good solution to realize a controlled Quadrature oscillator [17].The oscillator frequency can be adjusted by means of the value of the capacitor or the bias current of CCII 2,3 (the value of R eq ).However the capacitor values are not variable after integration, for this reason we present an ameliorate structure for the filter when we replaced the grounding capacitor by CMOS Varactors or by a multiplier capacitor [18].Figure 2 displays the architecture of the ameliorated filter.

The Optimized Differential Difference Translinear Current Conveyor
The DDCC is a four terminal active block.The symbol and the equivalent circuit of the the DDCC are illustrated in Figure 3.
The ameliorated all-pass filter.The DDCC ensures two functionalities between its te follower between terminals X and Z. (Yr to get ideal transfers, a DDCC should be ch rminals: In orde aracterized by low impedance on terminal X and high impedance on terminals Y 1 , Y 2 and Z.In this configuretion, the relation between terminal voltages and currents can be given by the following matrix: To realize this structure it's necessary to cascade C Voltage Buffer [3,4].The input tra MOS differential voltage buffer (DVB) with a CCII.An implementation of the CMOS differential voltage buffer (DVB) and the CCII are respectively shown in Figures 4 and 5 [2][3][4].

A. CMOS Differential
The (DVB) is shown in Figure 4 nsconductance elements are realized with two differential stages (M1 and M2, M3 and M4).The high gain stage is composed of a current mirror (M5 and M6).It converts the differential current to a single-ended output current (M7).The output voltage of this amplifier can be expressed as: where   Open Access CS

euristic methodology
To determinate the optimal transistor sizes (W and L) or this structure we will use the h f [6,7].This strategy consists on minimizing the impedance output value, assuming that the current mirror has unity gain and closer β y1 and β y2 to the unity.The output resistor is calculated as: Simulation conditions are summarized in Ta the resultant optimal transistor sizes (W and L) se ble 1 and are prented in Table 2.The optimized CMOS differential voltage buffer was simulated with Spice simulation in the ADS software.Main obtained results are represented in Figures 5 and 6. Figure 5 displays the DC transfer characteristics of the DVB.The voltage transfer can be linear between −0.6 V and 0.6 V.Moreover, the bandwidths of output terminals are shown in Figure 6.The −3dB bandwidths of   are located at 3.75 GHz.The time-domain response of the optimized DVB is shown in re 7. A sine wave of 100 mV and Figu −100 mV amplitude and 200 MHz is respectively applied as the input Y 1 and Y 2 to the filter.We notice that the output Waveforms are confused with the differential input Waveforms V y1 (t) -V y2 (t).This result confirms the good functionality of this structure.Table 3 shows the optimal device scaling that we get after applying the optimization approach.
The static and dynamic characteristics of r configuration are summarized at Table 4.

Simulation Results of the Proposed All-Pass Filter
The VM all-pass filter (Figure 1) is simulated SPICE program using 0.18 µm TSMC CMOS      shows the variability of the pole frequency of first-order all-pass buffer t with the bias current I o2,3 .The pole frequency can be contro in o2,3

Quadrature Oscillator Based on the Proposed All-Pass Filter
To illustrate the utility of the proposed filter (high input and low output impedances), no is required to connect it to the integrator circui ), it is connected in cascade to OS DCCIIs, tow CCII an integrator in a closed loop [17] to construct a quadrature oscillator, as shown in Figure 13.It is seen that the proposed architecture uses three optimized CM 's, one floating resistor and tow grounded capacitors.The corresponding characteristic equation is given by: This leads to the following oscillation co oscillation frequency respectively: ndition and
to Z (CCII+) is shown in Figure able 3 we give the different transistor size.

Figure 10 .
Figure 10.Gain and phase responses of proposed all-pass section.

Figure 11 .
Figure 11.Input and output waveforms for the circuit at 19 MHz.
of the quadrature oscillator can be seen in Figure14, showin the oscillator where C = 6 pF, C = 10 pF, R = 600 Ω,

Figure 14 .
Figure 14.The simulated quadrature output waveforms of V out1 and V out2 .The quadrature relationships between the generated waveforms have been verified using Lissagous figure and shown in Figure 15.

1 2 d
I o2,3 = 30 µA (R eq = R X2 + R X3 = 1.5 KΩ).The phase difference between two out puts V out1 and V out2 is 90˚ and the oscillation frequency is equal to 26 MHz (the theoretical value of the oscillation frequency is 30.5 MHz).

Figure 15 .
Figure 15.Lissagous figure.6.ConclusionIn this paper, we have proposed a new design of VM first-order all-pass filter.In order to get high perform ances of the fi d CCII struc tures are optimized in 0.18 µm CMOS process of TSMC.erified with the SPICE simu-