Conduction Mechanism Analysis of Inversion Current in MOS Tunnel Diodes

Self inversion issue and excess capacitance phenomenon were observed for the first time in relatively thick silicon dioxide (SiO2) in the form of MOS (metal(Al)/SiO2/p type crystalline silicon) structure. Both phenomena were based on minority carriers (electrons in this case) and studied through DC current-applied bias voltage (I-V) and AC admittance measurements in dark/light condition as a function of ambient temperature (295 380 K). Either of the cases was the departure of traditional MOS analysis, manifesting themselves in the inversion regime of MOS diode. Increase in frequency/temperature/light intensity within dark and light conditions led to weaken the maxima of hump in C-V curves and finally turned into deep depletion mode after exceeding threshold value of frequency/temperature/light intensity. In resumed conditions, supplementary I-V measurements were carried out to describe the generation and conduction mechanism(s) for minority carriers (electrons).


Introduction
Electrical properties of Metal-Oxide-Semiconductor (MOS) tunnel diodes, MOSTD, have been attractive due to technological and fundamental physical viewpoints.Though the scaling down of c-MOS integrated circuits leads to significant tunneling current and is a major concern, it also provides an opportunity to study transport phenomena in order to be utilized in light emitting diodes (LED) [1,2] photodetectors [3] and solar cells [4][5][6].
Inversion region is composed of minority carriers and measured inversion current of MOS diodes could be originated through band to bulk trap and/or band to band tunnelling, and interface state tunnelling [7,8].Self inversion in MOS structure beyond the gate electrode is a last minority carrier generation model [9][10][11][12][13].Usually, tunnelling rate and/or generation rate of minority carriers determine the amount of current flowing in MOSTD's where the semiconductor surface is inverted near zero bias [14,15].As the applied reverse bias increases, inversion regime becomes strong and hence tunneling current increases abruptly.In the forward direction, the semiconductor goes first from inversion to depletion and then depletion to accumulation regimes as applied bias is scanned from negative to positive bias side.The transition of defined regimes for MOS structure appears as a hump in current-bias voltage (I-V) curves and marks the semiconductor limited to tunnel limited behavior.This kind of hump in I-V curves is also observed in hydrogenated amorphous silicon (a-Si:H)/c-Si [16], micro c-Si/ c-Si [17], and silicon quantum dots embedded in SiO 2 insulator film/Si [18,19] structure.
Recently, Lin et al. [20] discussed the generation rate of electron-hole (e-h) pairs in Aluminum(Al)-SiO 2p/p + /p ++ -c-Si MOSTD's where p + /p ++ represents high doping concentrations of c-Si (above 10 18 cm −3 ).Their observations show that the generation rate of e-h pairs is mainly limited via band to traps tunneling and band to band tunneling rather than conventional Schockley-Read-Hall (SRH) statistic model [21,22].Noteworthy, the transition of band to bulk trap tunneling in depletion layer of c-Si into band to band tunneling through interface traps also exhibits a hump in both computed and experimentally determined I-V curves.Furthermore, band to traps and band to band tunneling models are identified by determining the value of activation energy (E A ) as well as their dependences on temperature/light illumination.Correponding to the hump in I-V curves, theoretical as well as experimental analysis of MOSTD's indicates similar hump behavior in capacitance-voltage (C-V) curves [7,8,14,15] in minority carrier devices.The onsets and breaking off of hump in capacitance correspond to the transition from semiconductor-limited to tunnel-limited behavior as in I-V curves.Moreover, it is explored that hump has both frequency and work function dependent on chosen metal as electrodes since metals having a low work function like magnesium (Mg) invert the insulator/semiconductor interface at zero bias [7,8,14,15].
This work discusses the self inversion issue and excess capacitance phenomenon observed for the first time in relatively thick insulator film within MOS structure.In self inversion, minority carriers pile up at SiO 2 /p-c-Si interface without applying external bias voltage.Those pre-existent electrons could be originated from either ion migration along the surface of insulator during application of prolonged bias voltage or proton diffusion adjacent to insulator/semiconductor interface within a moisture ambient.Due to the electrons, surface bands are bent, creating inversion regime without external bias voltage.Drastic influence takes place especially in this regime of MOS structure such that quasi-static C-V curve is observed for a huge ac modulation frequency (above 100 kHz).This kind of C-V behavior manifests itself as conductivity modulation in I-V measurement and getting such behavior is owing to the injection of minority carrier into the depletion region of junction.Consequently, an extra hole should be supplied to conserve the neutrality conditions, leading to change of the resistivity of diode.Such findings appear as conductivity modulation in I-V measurement and excess capacitance in C-V measurement.Within this context, integrated self inversion issue and excess capacitance phenomenon are considered to interprete anormal C-V feature in inversion regime of MOS structure at hand.

Film Fabrication and Experimental Tools
Boron doped and (100) oriented silicon (p-Si) wafer, grown by Czochralski method with 1 -3  cm resistivity and 400 µm thicknesses was cleaned chemically via RCA cleaning procedure prior to oxidation.SiO 2 insulator film was grown thermally at 1000˚C with dry oxygen (O 2 ) which flew with a constant rate of 600 sccm for 120 min.Backside was coated with Al when the system was pumped down to 10 −6 Torr.Then, wafer was annealed to have ohmic contact at 590˚C under N 2 ambient for 15 min.Finally, gate (front) electrode of the diodes was formed directly by evaporating Al through copper masks of diameter around 0.1 cm to obtain MOS structure.
For electrical analysis, I-V measurement was per-formed as a function of temperature in the range between 295 K and 380 K in dark/light condition by Keithley 6517A multimeter.Light illumination was carried out by tungsten lamp.In resumed conditions, capacitance (C) and conductance/frequency (G/ω) as a function of dc gate bias voltage (V G ) and its ac voltage modulation frequency (ω) were performed by HP4192A Impedance Analyzer (400 Hz to 1 MHz).Computer controlled LABWIEW program was facilitated to conduct measurements.The characteristic with Al as gate electrode demonstrates a consistent minority carrier behavior under small forward and reverse biases [7,8,14,15].As clear from Figure 1(a), three distinctly different conduction mechanisms are eventual under positively applied gate bias region: under low bias region where V is less than 1 V, sharp increase in current with applied voltage is observed.For the intermediate bias voltage region, 1 < V < 2.5 V, rate in increase reduces and becomes sharp again when V exceeds 3.5 V, exhibiting the onset of last conductive region.These regions illustrate the variation of transport mechanisms in dark I-V curve.Under weak (15 mW/cm 2 ) and strong light illumination (100 mW/cm 2 ), current in negative applied bias shows no drastic change.For the positive side, on the other hand, transition of one to another mechanism becomes smoother and subsequently light insensitive regions comes up around 7.5 V under dark/illuminated condition.In brief, temperature dependent I-V characteristics are required to determine governing generation/conduction mechanisms.

Temperature Dependent Current-Voltage Measurement
Figure 1(b) shows the small forwad dark I-V-T characteristics within the studied temperature interval of 295 -385 K.In junction limited case, measured current follows the diode equation: where I 0 = saturation current, A = temperature (in) dependent factor, k = Boltzman constant.Through fitting of I-V curves, I 0 and A are extracted and results are given in Table 1.Insignificant A variations with temperature are obvious.Moreover, Arrhenius plot of I 0 versus q/kT  [23].Dark I R -V R characteristic with temperature as parameter is given in Figures 1(c) and (d).In there, conductive regions become more clear than in Figure 1(a) where jump in measured current is eventual.For the first and second bias regions, I 0 vs q/kT leads E A as 0.68 and 0.25 eV, respectively.For the last region where V > 4V, the relation of I and V is described as where m depends on density of states.Such a characteristic behavior proposes space-charge-limited-current (SCLC) mechanism [24].Indeed, as given in Figure 1(d [20].That is the inversion current is comprised of thermal generating current and photo-generated current originated through interface traps and the traps in deep depletion region. Keep in mind that these mechanisms are competing under illumination and temperature dependence becomes insignificant when illumination intensity increases.Similar observations are made by us on relatively thick SiO 2 insulator film where film thickness is determined around 100 nm by high frequency C-V measurement on the Al/SiO 2 /p-c-Si/Ohmic Al MOS structure.Two competing mechanisms for electron/hole generation processes are observed under low illumination (15 mW/cm 2 ).Moreover, through Arrhenius analysis, E A is obtained around 1 eV from the low bias voltage side under illumination.However, once illumination intensity becomes strong (100 mW/cm 2 ), minority carriers due to light exposure becomes dominant and temperature increase within such condition is surpassed to create e-h pairs.The experimental findings as electron generating mechanisms as well as tunneling process at SiO 2 /p-c-Si interface are schematically illustrated in Figure 2. In dark, electrons are generated either through a bulk trap within depletion region by process A or over interface traps denoted as process B in Figure 2. Determined E A reveals that minority carrier generation takes place through the process A. In reverse bias, emerged electrons are directed towards SiO 2 and then flow by tunneling.In strong inversion, band to band tunneling occurs as proposed by Lin et al.Under light exposure, since E A is found around 1 eV, electrons seem to be excited to the conduction band directly.As inferred from dark/light illuminated I-V-T analysis, current transport mechanisms are unveiled that is nothing but predicted conduction paths in Figure 2. As a consequence of that described conduction paths yield excess capacitance issue in C-V measurement.Therefore, the subsequent section is devoted to debate C-V measurement within resumed condition to complete the analysis.Without frequency dependent, saturated capacitance and its reduction in value as gate bias grows towards more positive side is well known: the former corresponds to oxide capacitance, C ox (= ox A/d ox ) while decrease in its value is interpreted as the expansion of depletion layer.However, two minimum in inversion capacitance together with hump behavior at high frequency and quasi-static C-V feature as well as excess capacitance at "low" frequency (around 1 kHz) can not be explained as to conventional MOS theory.Room temperature C-V characteristics under high frequency are consistent with the published work on MOSTD's.Both hump behavior in C-V and inversion regime under zero bias are expected and experimentally observed on Al/SiO 2 /p-c-Si MOS minority carrier device.The former demonstrated the transition of semiconductor-limited to tunnel-limited behavior while the latter occurs because of low work function which inverts the interface of SiO 2 /Si structure.Additionally, frequency dispersion of the hump is also a characterictic feature in MOSTD's.

Characterization in
Self inversion issue is capable of explaining quasistatic C-V feature under high frequency in present diodes [10,21,22] and MOS diodes featuring silicon nanocrystals in SiO 2 matrix [18][19].In brief, self inversion is a coupling of internal and external inversion layers, respectively: the former is owing to applied inverting gate biases beneath the gate electrode and the latter is formed beyond the gate electrode and it is originated due to ion migration along the surface of insulator during application of prolonged bias voltage [10,21,22] and/or proton diffusion adjacent to insulator/semiconductor interface [25] within a moisture ambient.Consequently, gate electrode area fictitously is enhanced enormously, enlarging the capacity beyond the gate electrode, C D '.Since measured capacitance is in series combination of C ox and C D + C D ' [9][10][11][12][13], C ox is determined in C-V measurements.On the other side, this channel formation enhances the response time of minority carriers and hence the cutoff frequency of the channel becomes considerably higher than that for minority carriers under equilibrium.In other words, since the relaxation time (τ) of minority carriers would be the product of equivalent resistance and capacitance (τ = RC), minority carriers are in this case able to follow high frequency excitation (more than 50 Hz).As clear from Figure 3(a), this issue resolve only the first frequency dependent portion of the C-V curves in which capacitance rises at most C ox .Nevertheless, the capacitance exceeding C ox is abnormal in terms of MOS analysis and reported only by us as far as we know on MOSTD's.This kind of C-V behavior is reported in metal/semiconductor Schottky and p-n junctions in which semiconductor could be either crystalline or amorphous [26] phases.Provided that selfly inverted layer, MOS structure at hand can be considered as n/n + -p junction in which n/n + layer represent conducting channel at the vicinity of SiO 2 /Si interface connected in series to a bulk SiO 2 insulator film with an huge resistor.Within this frame, the picture matches with the case of intrinsic (i) a-Si:H/p-c-Si junction where (i) a-Si:H is slightly n-type doped with 10 9 Ω cm resistivity.[26].As bias changes from reverse to forward direction, diffusion capacitance makes a significant contribution over the depletion capacitance of the junction.In other words, diffusion capacitance is in parallel connection with depletion capacitance of the junction.Consequently, measured capacitance begins to increase in value due to the diffusion.As the applied bias increases towards a specific value so does the corresponding capacitance.At the proximity of the specific bias, the measured capacitance is in maxima; for further bias voltage, the capacitance starts to decline.Fall in capacitance from maxima marks the resistive part of a film where SCLC current mechanism is the governing conduction mechanism.Equivalent capacitance and conductance in junction limited case are described as where R j (R b ) is junction (bulk) resistance and C j (C b ) is junction (bulk) capacitance, respectively.In bulk limited case where SCLC current mechanism dominate the carrier conduction, decay in capacitance from maximum can be represented with the relation below: In other words, since depletion width becomes insignificant compared to film thickness in which bulk capacitance is ignored and bulk region is considered purely resistive.In turn, junction limited behavior switches into bulk limited one.The maxima of the hump around 0.9 V might represents either the barrier height of back Al metal electrode for electrons or band bending of SiO 2 / c-Si interface.1/C 2 -V G curves (given in Figure 3(b)) point both depleting type C-V character and temperature independent built in voltage.Hence, surface band bending should be in maxima.Furthermore, decay in capacitance from maxima corresponds to a well defined bias region (V G > 4 V) where SCLC mechanism is eventual (see Figure 3(b)).As clearly seen in Figure 4, the hump has also temperature/light intensity dependent as in modulation frequency.As ambient temperature/illumination intensity increases, the maxima occurs in lower capacitance valueswhile deep depletion regime in C-V G curves are formed.Within this context, excess capacitance issue, appears as hump in C-V curves under high frequency, is clearly related with current conduction mechanisms or electron generating mechanisms.Electrons due to illumination becomes pile up at the interface and forced to inject into SiO 2 film and reach to front electrode through SCLC mechanism.Furthermore, electrons are generated through band to band transition under illumination that is further verified by detemining E A (1.1 eV) through I-V-T measuments in light illuminations (see Figure 2).In admittance counterpart, since the trap loose its charge due to illumination, the electric field is terminated by the charges at the edge of depletion layer and hence deep depletion occurs solely in strong illumination.In dark condition, on the other hand, since the interface is inverted in both beneath and beyond of the gate electrode, the increase in gate bias in positive side do not change the amount of electron concentration but it would be counterbalanced by ionized dopant charges within the depletion layer and hence depletion region becomes widened.As it is widened, depletion capacitance decreases as does measured capacitance.

Conclusion
Anamolous C-V behavior at the inverting bias voltage on Al/SiO 2 /p-c-Si/Ohmic Al MOS tunnel diode was discussed in terms of self-inversion and excess capacitance issues for the first time.These phenomena were capable of exploring unusual C-V features at inverting bias region in which inversion tunneling current in dark ambient was dominated by the thermal generation rate of  electron-hole couple through interface traps and bulk traps, lying in the depletion region of p type crystalline silicon.

Figure 1 (
Figure1(a) depicts the I-V variation of Al/SiO 2 /p-c-Si/Ohmic Al MOS tunnel diode in dark and different intensity of light exposure at room temperature.The characteristic with Al as gate electrode demonstrates a consistent minority carrier behavior under small forward and reverse biases[7,8,14,15].As clear from Figure1(a), three distinctly different conduction mechanisms are eventual under positively applied gate bias region: under low bias region where V is less than 1 V, sharp increase in current with applied voltage is observed.For the intermediate bias voltage region, 1 < V < 2.5 V, rate in increase reduces and becomes sharp again when V exceeds 3.5 V, exhibiting the onset of last conductive region.These regions illustrate the variation of transport mechanisms in dark I-V curve.Under weak (15 mW/cm 2 ) and strong light illumination (100 mW/cm 2 ), current in negative applied bias shows no drastic change.For the positive side, on the other hand, transition of one to another mechanism becomes smoother and subsequently light insensitive regions comes up around 7.5 V under dark/illuminated condition.In brief, temperature dependent I-V characteristics are required to determine governing generation/conduction mechanisms.

Figure 3 (
Figure3(a) displays dark capacitance-gate bias (C-V G ) variation as a function of modulation frequency (0.7 kHz-1 MHz) of the present diode at room temperature.The insets of Figure3(a) displays "low" and high frequency C-V G variations.As gate bias is scanned from more negative to more positive side, frequency/bias independent saturated capacitance begins to decrease.Without frequency dependent, saturated capacitance and its reduction in value as gate bias grows towards more positive side is well known: the former corresponds to oxide capacitance, C ox (= ox A/d ox ) while decrease in its value is interpreted as the expansion of depletion layer.However, two minimum in inversion capacitance together with hump behavior at high frequency and quasi-static C-V feature as well as excess capacitance at "low" frequency (around 1 kHz) can not be explained as to conventional MOS theory.

Figure 1 .
Figure 1.(a) Current-applied gate bias variation of Al/SiO 2 /p-c-Si/Ohmic Al MOS structure in dark and different intensity of light exposure at room temperature.(b) Dark current-bias voltage variation as a function of temperature in between 295 K and 380 K. Solid lines are fitted to experimental data and indicate temperature invariant factor, denoted as A in the body of the work.(c) Dark reverse current-reverse bias characteristic with temperature as parameter.Variation of conduction mechanisms appear as jump in the curves.Also note that fits to experimental data (solid lines) are temperature invariant.(d) Log-log plot of current-bias voltage characteristics within studied temperature interval for V R > 4 V.All fits (solid lines) showed a constant bias power (m) with greater than 2.

Figure 2 .
Figure 2. Schematic illustration of minority carrier conduction path, denoted as A through bulk trap in depletion region and B via interface traps.Equivalent circuits display self inversion in MOSTD's and excess capacitance for n-p junction.Note also that R c and R f represent internal/external inversion layers.

Figure 3 .
Figure 3. (a) Dark C-V characteristic as a function of modulation frequency.The inset of figure display "low" and high frequency C-V characteristics.Note that main frequency dependent regions correspond to self inversion issue and excess capacitance phenomenon, respectively.Except this departures, present diode indicates a traditional MOS regimes; accumulation, depletion, inversion and deep depletion.(b) Dark C −2 versus V variation as a function of ambient temperature at 1 MHz.

Figure 4 .
Figure 4. C-V variation as a function of temperature in dark (a) and (b) various light intensities under constant frequency (100 kHz).In (c), "low" C-V variation as in (b).