Logical Function Decomposition Method for Synthesis of Digital Logical System Implemented with Programmable Logic Devices (PLD)

The paper consists in the use of some logical functions decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix calculation. It is calculated the implementation costs emphasizing the most economical solutions. One important aspect of serial decomposition is the task of selecting “best candidate” variables for the G function. Decomposition is essentially a process of substituting two or more input variables with a lesser number of new variables. This substitutes results in the reduction of the number of rows in the truth table. Hence, we look for variables which are most likely to reduce the number of rows in the truth table as a result of decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input variables. The only available parameter to evaluate its activity is the number of “l”s or “O”s that it has in the truth table. If the variable has only “1” s or “0” s, it is the “best candidate” for decomposition, as it is practically redundant.


Introduction
In the implementation of logical functions we are looking to optimize some parameters such as the propagation time, cost, areas, power, etc.The decomposition problem is old, and well understood when the function to be decomposed is specified by a truth table, or has one output only.However, modern design tools handle functions with many outputs and represent them by cubes, for reasons of efficiency.We develop a comprehensive theory of serial decompositions for multiple-output, partially specified, Boolean functions.A function  1 , , n  , , , , ,  of input variables, and g and h have fewer inputvariables than f.
It is sometimes the case that a set of Boolean functions cannot be made to fit into any single module intended for its implementation.The only solution is to decompose the problem in such a way that the requirement can be met by a network of two or more components each implementing a part of the functions.The general pro-blem can be stated as follows.The set of functions to be implemented quires a logic block with N inputs and M outputs.The decomposition task is to design a network which will implement the function using blocks with a maximum of n inputs and m outputs, where n < N or m < M.
(A) Initially, we will consider a decomposition algo- rithm of logical functions [1].
and p Boolean functions denoted by , it is possible to decompose the function f depending on     ?In other words, there is a function F so that , , ; , , , , (1.1) (the empty set).
We will call this proceeding, Type I problem.1.2.Given a Boolean function , , ; , , , , , where and 2 have the same meaning as in 1.1.We will call this proceeding, the type II problem.
(B) Matrices related to Boolean functions.The image of a logical function [1] It defines the image of a logical function the Boolean row array that represents the values of this function, ordered by truth table .For example, has the following truth table: Considering the above, we can write We can verify the following properties: To a function can be attached a Veitch matrix, for the previous case being:

The Representation of a Boolean Function Using Subfunctions. The R JI Matrix
Let's consider a function G of two subfunctions f 1 and f 0 that depend on the Boolean variables 2 1 0 , , x x x and on the two variables 4 3 , x x : After a simple calculation is deduced the image of function G.
We suppose that the images of the two subfunctions are: that means: Starting from the expressions of G, f 1 and f 0 can be calculated: The image of function F is calculated below: The Veitch tables relating to the G and F functions are: Note that the E matrix has only four distinct columns that are found in E matrix.
In [1], it demonstrates that for the function F it can be attached a pseudo-unitary matrix denoted by R JI in which in each column the logic digit 1 corresponds to the E column's order number, therefore: In [1] is also demonstrated the relation: Therefore, the decomposition of a function in subfunctions is reduced to solving the following Boolean equations: [1] a) Let's consider X a some matrix.It is valid the relation (2.12), [1].
 B (t A -the transpose of the matrix A) (2.12) b) Let's consider X a pseudo-unitary matrix.It is valid the relation (2.13) [1].
, there is no solution for the matrix X.In this case it is trying to solve the following equations: (the previous solution) or (2.17) (the consequence solution).We will return to these problems in a future paper.

Examples
(A) Let's consider the function defined by , , , , 0,3,5, 6,9,10,12,14,15,16,17,18,19, 21, 22,30 Applying the Veitch-Karnaugh method [2], a minimal form is given by the expression: We define the cost of implementation as the number of the inputs in the basic circuits, components [3].In the previous case, by implementing with AND-OR circuits, results: . (It is considering that the input variables are provided inverted and non-inverted, i.e. , i i x x .)Let's consider the following possible decomposition: . For the function F corresponds the following Veitch matrix, denoted by E: Matrix E having four distinct columns, a solution for E is: Therefore, the matrix R JI , solution of the equation From where we obtain: or after an elementary calculation: Using E' matrix we obtain: with a possible implementation as in Figure 1.
So, we will have: Open Access CS (B) Implementation using programmable logic devices (PLD) We will consider a circuit PAL10L8 [4], which has 10 inputs, 8 outputs and having an AND-OR configuration, each NOR having 2 inputs, with the structure illustrated in Figure 2.
Let's consider the previous function: We will use the following algorithm: Therefore, Will be needed: 9-product terms , , so it will be used 16 product terms from maximum 20.But the number of inputs is insufficient (see Figure 3).
Classic, we should also use two circuits (PAL10L8), or a single circuit with greater capacity.
Let go back to the same function that uses the subfunctions f 1 , f 0 , which have the expressions: , , , , , , , Therefore, after a preliminary evaluation we have: 4 product terms   1 0 , f f and 5 product terms for function G.
Let's consider , where a i are the terms of the decomposed function.A PAL implementation is like in Figures 3 and 4.  A possible implementation would be (see Figure 4):

Decomposition into EMB Blocks
The single step of the functional decomposition replaces function F with two subfunctions [5].This process is recursively applied to both the G and H blocks until a network is constructed where each block can be directly implemented in single logic cell of target FPGA architecture.
Logic cell can implement any function of limited input variables (typically 4 or 5).Thus the main effort of logic synthesis methods based on decomposition is to find such partition of input variables into free set and bound set that allows creating decomposition with block G not exceeding the size of logic cell.Various methods are used, including exhaustive search since the size of logic cell is small.It should be noted that the main constraint is the number of inputs to block G and not the number of outputs.This is because block G with more outputs than in logic cell can be implemented with use of few logic cells used in parallel.Since EMB blocks can be configured to work as logic cell of many different sizes [6], approach known from methods targeted for logic cells is not efficient.The main reason is that the method must check decomposition for many different sizes of block G.The second factor is that in case of EMB the efficiency of utilization of these blocks depends on carefully selected size of block G.For example M512 RAM block of Stratix device can be configured among others as 8 input and 2 output logic cell or 7 input and 4 output logic cell.Let assume that in decomposition search following solutions are possible: block G with 8 inputs and 1 output or block G with 7 inputs and 3 outputs.From the EMB utilization point of view the second solution is better, since it utilizes 384 bits of total 512 bits available, while the first solution utilizes only 256 bits.R-admissibility is used to evaluate serial decomposition possibilities for different sizes of G block according to possible configuration of EMB blocks.Since EMB can be configured as a block of many different sizes the possible solution space is large.Using Property 1 the search can be drastically reduced.This will be explained in the following example.
Example.R-admissibility application to serial decomposition evaluation.For function from Example 1 we have that the admissibility of single input variables 1 , , , V x x x x  should be evaluated.We have: This means that for such variable partitioning decomposition may exist with block G having 1 output.With this approach to serial decomposition, there is no difference between disjoint and non-disjoint decomposition in their calculation.Particularly, it can be concluded that for finding blanket G we can simply apply the method of calculating compatible classes of βV blocks [7] which was recently improved in [8].

Conclusions
The paper represents the "rediscovery" of some decomposition algorithms of Boolean logic functions, using subfunctions [1].
After a brief exposure of the decomposition methods of Boolean logical functions, the authors, through the proposed example, shows the reduction of the implementation cost using standard logical circuits.
The authors show that when using PLD circuits, the use of Boolean functions decomposition method reduces the number of circuits necessary for the implementation (see PAL10L8).
Balanced decomposition proved to be very useful in implementation of combinational functions using logic cell resources of FPGA architectures.However, results presented in this paper show that functional decomposition can be efficiently and effectively applied also to implement digital systems in embedded memory blocks.Application of r-admissibility concept makes possible fast evaluation of decompositions for different sizes of block G.This allows selecting best possible decomposition strategy.
The paper showed that the use of Boolean functions decomposition method reduces the number of circuits necessary for the implementation.However, this substitution process reduces the circuits cost by increasing the circuit complexity, which also enhances the likelihood of errors in the circuit design.
Balanced decomposition proved to be very useful in implementation of combinational functions using logic cell resources of FPGA architectures.However, results presented in this paper show that functional decomposition can be efficiently and effectively applied also to implement digital systems in embedded memory blocks.

Figure 1 .
Figure 1.The implementation of the function F, using subfunctions.

Figure 4 .
Figure 4.A possible implementation of PAL10L8 circuit.
When considering solutions with 4 inputs to block G, according to Property 1,[7,8] only solution with