A CMOS 3 . 1-10 . 6 GHz UWB LNA Employing Modified Derivative Superposition Method

Low noise amplifier (LNA) performs as the initial amplification block in the receive path in a radio frequency (RF) receiver. In this work an ultra-wideband 3.1 10.6-GHz LNA is discussed. By using the proposed circuits for RF CMOS LNA and design methodology, the noise from the device is decreased across the ultra wide band (UWB) band. The measured noise figure is 2.66 3 dB over 3.1 10.6-GHz, while the power gain is 14 ± 0.8 dB. It consumes 23.7 mW from a 1.8 V supply. The input and output return losses (S11 & S22) are less than –11 dB over the UWB band. By using the modified derivative superposition method, the third-order intercept point IIP3 is improved noticeably. The complete circuit is based on the 0.18 μm standard RFCMOS technology and simulated with Hspice simulator.


Introduction
Development of the high-speed wireless communication systems puts increasing request on integrated low-cost RF devices with multi-GHz bandwidth operating at the lowest power consumption and supply voltage.Ultra wide band (IEEE 802.15.3a) appears as a new technology capable for high data transfer rates (up to 1 Gb/s) within short distances (10 m) at low power.This technology uses for some application such as wireless personal area networks (WPANs), providing an environment for transmission of audio, video, and other high-bandwidth data [1].The amplifier that is used for this application must meet several requirements.For example to interface with the preselect filter and antenna, the amplifier input impedance should be close to 50 over the desired UWB band.However sufficient gain with wide band width to overtop the noise of a mixer, low noise figure to improve receiver sensitivity, low power consumption to increase battery life, small die area to reduce the cost, unconditional stability and good linearity are important parameters.There is a close trade-off between them.There are some proposed solutions and circuits for each parameter [2][3][4][5][6][7][8].However, some parameters would be ruined by improving the others [4].In this research a new circuit has achieved via modifying these methods [1,9].The main parameter in this research is noise figure which has noticeably improved in comparison with the other references.It is 2.66 -3 dB over 3.1 -10.6-GHz band width.

Input Stage
Common-gate and Cascode configurations are two kinds of methods usually used to design the input stage of LNA in CMOS circuits, while the Common-Gate and Cascode structure provides a wide-band and narrow-band input matching respectively.However Common-gate stage has an intrinsically high noise figure versus Cascode stage and the noise-canceling techniques must be used.In the narrow band application, a shunt inductor is added in the input stage to resonate with C gs to enhance impedance matching at the desired frequency.However in most CMOS narrow band applications, cascode LNA with inductive degeneration is preferable but for isolating from the input to the output and omitting of the C gd path, the Common-Gate LNA performs better reverse isolation and stability versus Common-Source LNA.
Numerical value for the lower bound is about 2.2 dB for long-channel devices and 4.8 dB for short channel devices.

Circuit Design and Analysis
The proposed wide-band LNA is shown in Figure 1.It consists of an input stage and a cascode second stage.An off-chip bias-T provides the gate bias of M 3 and the DC current path of M 1 .The series inductors L 1 and L 3 further resonate with the input gate-source capacitance of M 4 and M 6 respectively, resulting in a larger bandwidth and some residual peaking on the frequency response [10].The parasitic capacitances of M 1 and M 3 make an LC ladder structure with inductor L 0 .The DC load resistors R 1 and R 2 are combined with shunt peaking inductors L R1 and L R2 respectively to extend circuit bandwidth effectively [11].The series peaking inductor L R2 also resonate with the total parasitic capacitances C d2 and C d3 at the drain of M 2 and M 3 .Since the load resistor, R 3 , is added to reduce the Q factor of L R3 for flat gain and can be directly substitute for a switching quad to form a single-balanced mixer then the output 50 ohm matching is not demanded in an integrated receiver.The minimum channel length of 0.18 μm is considered for all the transistors in the proposed circuit to minimize parasitic capacitances and improve frequency performance.The Cascode stage extends bandwidth, provides better isolation and increases frequency gain.In fact the input stage and the Cascode stage support low-frequency power gain and high-frequency power gain, respectively.The combination of both frequency responses lead to a broadband power gain.
Table 1 shows the design values of the proposed CMOS LNA.

Input Common-Gate Stage and Noise Issues
In Figure 2 the simulated NF and S11 parameter is compared to the case with M 1 is turned OFF.There is a close tradeoff between NF and S11.When M 1 is turned on, the NF is increased by at least 0.6 dB and S21 parameter is decreased 2 dB with the same power dissipation and a similar bandwidth, but on the contrary an acceptable input matching will be achieved.Although the  transistor M 1 provides a wide-Extra band matching, it has an intrinsically high noise figure.In order to investigate the noise performance, the MOS transistor noise model with the channel thermal noise is used.As shown in Figure 3, neglecting gate and flicker noises and assuming a perfect match in this analysis, the PSD of the channel thermal noise 2 , where k is the Boltzmann constant, T is the absolute temperature in Kelvin,  is the MOS transistor's coefficient of channel thermal noise, α is defined as the ratio of the transconductance g m and the zero-bias drain conductance g ds and f is the bandwidth over which the noise figure is measured respectively.If the condition ( 2) is established the noise of the M 1 is omitted [1].
The following equations describe the noise figure by R 1 , M 2 and M 3 that they contribute to the overall noise figure.
Thus, the total noise figure can be approximated as ( 6)

Simulation Result
The circuit was simulated with 0.18 μm TSMC library Hspice simulator.All simulations are done considering 50 Ω input and output terminals.In Figure 4 S parameter are simulated.S11 and S22 are approximately less than −11 dB.The average gain power is approximately 14 dB with 0.8 dB ripple over the frequency range and the reverse isolation is less than −33 dB.

Modified Derivative Superposition Method for Linearizing
In this section by using the modified derivative superposition method [9], the linearity of LNA will be improved,  and IIP3 will be increased over the UWB band.The small-signal output current of a common-source biased in saturation region can be expressed as where g 1 is the small-signal transconductance and the higher order coefficients (g 2 , g 3 , etc.) explain the strengths of the corresponding nonlinearities [9].Among these coefficients, g 3 is the most important parameter because the third-order inter modulation distortion (IMD3) depends it and thus determines IIP3.The coefficients of ( 7) can be derived as ( 8) when gs crosses from the weak and moderate inversion regions to the strong inversion (SI) region, g 3 changes from positive to negative [12].If a positive g 3 with a specific g 3 (VGS) curvature of one MOSFET is aligned with a negative g 3 with a similar, but mirror-image curvature of another MOSFET by offsetting their gate biases, and the g 3 magnitudes are equalized through a relative MOSFET scaling, the theoretical AIP3 will be efficiently improved in a wide range of the gate biases and the resulting composite g 3 will be close to zero [9].As sho v wn in Figure 5 at the optimum gate biases, w tive su m hen two FET are paralleled and one of them operates in the weak inversion (WI) region near the peak in its positive g 3 and another works in the SI region near the dip in its negative g 3 , the achieved AIP3 will be improved.
Figure 6 presents the effect of modified deriva perposition method on the similar circuit [9].By using this method IIP3 increases notably across the UWB band.
Figure 7 shows the effect of using modified DS ethod on the IIP3 versus frequency respectively.If the M 6 is omitted the IIP3 change as Figure 7 but other parameters do not change considerably.

CS
The results of this work are shown in Table 2 and are compared with recently published CMOS LNAs.

Conclusion
This paper presents a new design of an UWB LNA structure based on a standard RFCMOS technology.Satisfactory input matching and noise performance are obtained after regarding the tradeoff between the input impedance of the common-gate stage and its noise performance.The measured noise figure is 2.66 -3 dB over 3.1 -10.6-GHz that is noticeable in comparison with the other references.A flat gain is worth mentioning in all LNA design and the simulated power gain is 14 ± 0.8 dB.

Figure 2 .
Figure 2. Simulated noise figure and input isolation with M 3 turned ON and OFF.

Figure 3 .
Figure 3. Principle of the noise schematic.

Figure 5 .
Figure 5. Modified derivative superposition meth d for o linearizing.