Efficient Time-Domain Signal and Noise FET Models for Millimetre-Wave Applications

Based on the active coupled line concept, a novel approach for efficient signal and noise modeling of millimeter-wave field-effect transistors is proposed. The distributed model considers the effect of wave propagation along the device electrodes, which can significantly affect the device performance especially in the millimetre-wave range. By solving the multi-conductor transmission line equations using the Finite-Difference Time-Domain technique, the proposed procedure can accurately determine the signal and noise performance of the transistor. In order to demonstrate the proposed FET model accuracy, a distributed low-noise amplifier was designed and tested. A model selection is often a trade-off between procedure complexity and response accuracy. Using the proposed distributed model versus the circuit-based model will allow increasing the model frequency range.


Introduction
Efficient Computer-Aided Design (CAD) of high-frequency systems is critically based on the performance of their internal component models.As the core of modern communication systems, active devices should be then carefully modeled for reliable system design.In high frequencies, when the device physical dimensions become comparable to the wavelength, the input active transmission line has a different reactance from the output transmission line [1,2], exhibiting different phase velocities for the input and output signals.Therefore, the phase cancellation due to the phase velocity mismatching will affect the device performance [3].Thus, a full-wave timedomain analysis involving distributed elements should be considered.However, this type of analysis is highly time consuming [4][5][6], even if different simulation time reduction techniques have been already proposed [7].As a result, semi-distributed models such as the slice model could be seen as a suitable alternative to overcome this limitation [8].However, by increasing the frequency up to the millimetre-wave range, the slice model cannot precisely model the wave propagation effect and phase cancellation phenomena.Therefore, to achieve more accurate design in millimetre-wave applications, one needs to develop a more advanced distributed model.
In this paper, a distributed model is proposed [9].It includes the effect of wave propagation along the electrodes more accurately than the semi distributed model although the CPU time of this model is a little higher than the slice model.Since a time domain analytical solution does not exist, a numerical approach was used.Among all the existing methods, the Finite-Difference Time-Domain method (FDTD) was retained as one of the most widely used in this area [10].The proposed model was demonstrated through the design of a distributed amplifier.

Signal FET Modeling
The proposed millimetre-wave Field Effect Transistor (FET) model is shown in Figure 1.It consists of three active coupled transmission lines (i.e., the three coupled electrodes of the device).As shown in this Figure, each elementary section x of the model can be represented by a 6-port equivalent circuit.This approach combines a conventional FET small-signal equivalent circuit model with a distributed circuit to account for the coupled transmission line effect of the electrode structure where all parameters are per unit length.With the condition Δx → 0, we obtain the following system of equations [11,12]: , , , , 0 and where V d , V g , and V s , are the drain, gate and source voltages, respectively, and g V the voltage across gate-source capacitor.I d , I g , and I s are the drain, gate and source currents, respectively.These variables are timedependant and function of the position x along the device width.Also, M ds , M gd , and M gs represent the mutual inductances between drain-source, gate-drain and gatesource, respectively; In the above system, we have an extra unknown parameter, i.e., the gate-source capacitance voltage  g V  .Therefore, the following equation should be included to complete the system of equations

Noise FET Modeling
Similarly to the signal model proposed in the above section, a noise model can be developed based on the same concept, i.e., a set of transmission lines excited by noise equivalent sources distributed on the conductors, as shown in Figure 2. We thus have where Note that the vectors [v n ] and [j n ] in Figure 2 are the linear density of exciting voltage and current noise sources, respectively.
To evaluate the noise sources, we considered a noisy FET subsection with gate width Δx.Thus, the unit-perlength noise correlation matrix for chain representation of the transistor (CA UPL ) can be deduced as [13]  where < > denotes the ensemble average and + the transposed complex conjugate.According to the correlation matrix definition, we can calculate [v n ] and [j n ] knowing (CA UPL ), to completely describe the proposed FET noise model.Indeed, by solving (9), the noise parameters of the transistor can be obtained.
Based on the transmission line circuit theory, the model impedance and admittance matrices can be expressed as and [G] refer to the matrix representation of the well-known distributed circuit parameters of a transmission line namely, the resistance R, the induc-tance L, the capacitance C, and the conductance G, respectively.[Y tr ] is accounted for the active parallel sub-section of the model.By solving the second-order differential equations of the model, its voltage and current vectors can be written as [14]  where represent the voltage and current vectors at the transistor terminals, respectively (Here d, g, and s stand for drain, gate and source, respectively).The superscript "t" refers to the vector transpose.Let the elements of matrix [] be the eigenvalues of

and the elements of matrices [S v ] and [S i ] be the eigenvectors of [Z]•[Y] and [Y]•[Z]
, respectively [16].By considering the boundary conditions of the six-port model, the unknown coefficients V  and V  can be determined.Then, applying (11) and ( 12) for x = 0 and x = w, w being the gate width, the voltages and currents of each port can be obtained, leading to the 6 * 6 impedance    l 6 6 Z   and admittance matrices of the model, which can be easily transformed to the scattering matrix form.Y 

The FDTD Formulation
The FDTD technique was used to solve the above equations.Applications of the FDTD method to the full-wave solution of Maxwell's equations have shown that accuracy and stability of the solution can be achieved if the electric and magnetic field solution points are chosen to alternate in space and be separated by one-half the position discretization, e.g., Δx/2, and to also be interlaced in time and separated by Δt/2 [15][16].To incorporate these constraints into the FDTD solution of the transmission-line equations, we divided each line into Nx sections of length x, as shown in Figure 3. Similarly, we divided the total solution time into segments of length Δt.In order to insure the stability of the discretization process and to insure second-order accuracy, we interlaced the Nx + 1 voltage points, Applying the finite difference approximation to (7) gives for the drain electrode for the gate electrode for the source electrode, where k, m and n are integers.Solving these equations gives the required recursion relations Superposing all the distributed noise sources is equivalent to a summation in (21) and ( 22) over the gate width for .Because of its simplicity, the leapfrog method was used to solve the above equations [13,14].First the voltages along the line were solved for a fixed time using (21) then the currents were determined using (22).The solution starts with an initially relaxed line having zero voltage and current.

Transistor Noise Correlation Matrix
To find the noise correlation matrix for admittance representation of the transistor as a noisy six-port active network (as in Figure 2), the values of port currents should be determined when they are all assumed shortcircuited simultaneously.Equation (21) for k = 0 and k = Nx + 1 becomes   By considering Figure 3, this equation requires that we replace Δx by Δx/2 only for k = 1 and k = Nx+1.
In order to determine the transistor noise parameters, we set the input voltage source as zero (V s = 0).Referring to Figure 4, we denoted the currents at the source point (x = 0) as I 0 and at the load point (x = L) as I Nx+1 .To determine the currents I 1 and I Nx at short-circuited ports (x = 0 and x = L), we set V 1 = V Nx+1 = 0.The finite difference approximation of (23) for k = 1 and k = Nx can be then written as (25) and (26), respectively.
The admittance noise correlation matrix of the six-port FET noise model is then equal to Finally, the currents of the short-circuited ports can be determined as

Numerical Results
The proposed approach was used to model a sub micrometer-gate FET transistor (NE710).The device has a 0.3 × 560 μm gate.The input and output nodes were with connected to the beginning of the gate electrode and at the end of the drain electrode, respectively.The transistor was biased at V ds = 3 V and I ds = 10 mA.The obtained S-parameters of the transistor over a frequency range of 1-26GHz from the sliced model, the proposed fully distributed model and measurements are plotted in Figure 5.
As expected, our distributed model is more close to measurements than the slice model, especially at the upper part of the frequency spectrum, when the device physical dimensions are comparable to the wavelength.Figure 6 shows the noise figure obtained for three different sets of data.
To further prove the accuracy of the proposed wave approach in noise analysis, our results were successfully compared to measurements as well as to those obtained by the sliced model, highlighting the advantage of our model over this later (Figure 7).Thus, the proposed wave analysis can be applied for accurate noise analysis of FET circuits.

Amplifier Design and Analysis
To validate our proposed FET model, a three stage distributed FET amplifier was designed.In this work we considered a Pi-gate FET transistor suitable for low-noise applications.The topology of the gate and drain lines for transmission line modeling is shown in Figure 8 while the amplifier layout is shown in Figure 9.
The obtained power gain and minimum noise figure of the amplifier are shown in Figures 10 and 11, respecttively.As we observe there is good agreement between the proposed model and measurements as compared with the sliced model.

Conclusion
A new modeling approach for signal and noise analysis of high frequency transistors was presented.This method can accurately take into account the effect of wave propagation along the device electrodes.The promising model can be applied to solve issues related to simultaneous signal and noise analysis, as well as in modeling traveling wave FETs in which the gate width is much higher than that of a usual FET

Figure 1 .
Figure 1.The different parts of a segment in the distributed model.

Figure 2 .
Figure 2. Noise-equivalent voltage and current sources.
voltage and adjacent current solution points were separated by Δx/2.In addition, the time points were also interlaced, and each voltage time point and adjacent current time point were separated by Δt/2 [17,18].Then, (8) can lead to

Figure 3 .
Figure 3. Relation between the spatial and temporal discretization to achieve second-order accuracy in the discretization of the derivatives.

Figure 4 .Figure 5 .
Figure 4. Voltage and current solution points.Spatial discretization of the line showing location of the interlaced oints.p

Figure 6 .
Figure 6.Comparison between normalized equivalent noise admittance and noise figure of FET for sliced, proposed distributed model and measurements.

Figure 7 .
Figure 7.Comparison between the results of slice modeling, proposed model and measured values of amplitude and the phase of optimum reflection coefficient.

Figure 10 .
Figure 10.Power gain comparison for measured, proposed model and sliced model for distributed amplifier.

Figure 11 .
Figure 11.Minimum noise figure comparison for measured, proposed model and sliced model for distributed amplifier.