An Analytical Approach for Fast Automatic Sizing of Narrow-Band RF CMOS LNAs

We introduce a fast automatic sizing algorithm for a single-ended narrow-band CMOS cascode LNA adopting an inductive source degeneration based on an analytical approach without any optimization procedure. Analytical expressions for principle parameters are derived based on an ac equivalent circuit. Based on the analytical expressions and the power-constrained noise optimization criteria, the automatic sizing algorithm is developed. The algorithm is coded using Matlab, which is shown capable of providing a set of design variable values within seconds. One-time Spectre simulations assuming usage of a commercial 90 nm CMOS process are performed to confirm that the algorithm can provide the aimed first-cut design with a reasonable accuracy for the frequency ranging up to 5 GHz. This work shows one way how accurate automatic synthesis can be done in an analytical approach.


Introduction
In the field of RF transceiver design, there is a strong demand to digitalize even RF analog parts to mount a transceiver on a single chip [1,2] to utilize the capability of automatic synthesis in digital circuit design.However, the low noise amplifier (LNA), which is a critical building block in any RF front-end, is not ready for digitalization yet.Many efforts have been done for design automation of LNA beforehand since the design of LNA is a time-consuming task that typically relies heavily on the experience of RF designers.LNA design automation can significantly simplify the design task, and also opens a possibility towards digitalization.
There are two basic methods for LNA design automation: simulation based or equation based.Although the simulation-based methods [3,4] are more accurate, they are time consuming due to optimization procedures.On the other hand, equation-based methods [5][6][7] are faster, but are dependent on the accuracy of the models used.To overcome the disadvantages in some extent, advanced methods using both of equation-based and simulationbased approaches [8][9][10] have been also suggested.
The difficulties in design automation of LNA lie in several aspects.It is topology dependent, and the design itself is difficult involving trade-offs among critical figures of merits such as NF, power gain, impedance matching, power consumption, linearity, and stability.Mentioning the difficulties in a manual design, for example, even only for input and output matching, many iteration steps are needed.It should be also redesigned every time when the fabrication process is changed.Therefore it is desirable if the first-cut design synthesis can be done automatically and fast with an acceptable accuracy.
The purpose of this work is to suggest a methodology for providing a set of first-cut design variables for a narrow-band LNA with a reasonable accuracy once design and process specifications are given.
We introduce a speedy automatic sizing algorithm for a single-ended narrow-band cascode LNA adopting inductive source degeneration based on an analytical approach without any optimization procedure.In Section 2, design assumptions are discussed.In Section 3, analytical expressions for principle parameters are derived based on an ac equivalent circuit assuming a resistive output termination.In Section 4, the developed automatic sizing algorithm is explained in detail.In Section 5, verifications are given to check the accuracy of the automatic sizing results.
structure with an inductive source degeneration shown in Figure 1 is the most attractive one in single-ended topologies since it gives smaller input capacitance and larger in-out isolation [11].In this work, the cascode LNA topology shown in Figure 1 is chosen as the objective circuit for automatic sizing even though the same approach can be applied to the other topologies.
There are several assumptions made in this work as follows: 1) Narrow-band LC matching networks are used for input and output as shown in Figure 1.R 1 is used to provide capability for adjusting power gain.As the output termination, two cases are considered: resistive or capacitive termination.
2) For sizing of the MOS transistors M 1 and M 2 , the power-constrained noise optimization (PCNO) criteria [11] is adopted to trade off noise performance against power consumption.
3) Ideal inductors and capacitors are used by assuming usage of off-chip components.The series resistances of the on-chip inductors can be considered as well, but we choose a simpler case.
4) A current-mirror biasing is adopted as shown in Figure 1.
5) The widths of M 1 and M 2 are set as same.
6) The design specifications include operating frequency, input and output terminations, power consumption, power gain, and sufficiently low input and output reflection coefficients S 11 and S 22 .
7) The design variables include L g , L s , L 1 , C i , C o , R 1 , R DB , and R B including the widths of M 1 , M 2 , and M B in Figure 1.

Derivation of Analytic Expressions for
Principal Parameters

Input Impedance
Figure 2 is the whole ac equivalent circuit for the cascode LNA shown in Figure 1 including the input signal source and the output resistive termination.We note that, compared to the complete equivalent circuit of the BSIM4 NMOS transistor in SPICE, only the back-gate transconductance g mb and the gate-body capacitance C gb in the transistor model are ignored to simplify the analysis.The distributed resistances including R s , R d , R g , and R sub , which are included in the BSIM 4 transistor model, are also ignored since they are negligible in large transistors.
In Figure 2, g m1 and g m2 denote the transconductances of M 1 and M 2 , respectively.C gs , C gd , and C ds denote the gate-source, gate-drain, and drain-source capacitances of the NMOS transistors, respectively.C js and C jd denote the source-body and drain-body junction capacitances, and C L is equal to the sum of C dg2 and C jd2 , which are the capacitances present at the drain node of M 2 in Figure 1.
The impedances Z in , Z in1 , Z in2 , Z o , Z out , Z out1 , and Z out2 are self-defined in the circuit.We first consider the resistive output termination case and discuss the capacitive output termination case later in Section 6.We note that C gs , C gd , and C ds are replaced by C sg , C dg , and C sd , respectively, in some part of our derivations for input and output impedances considering the non-reciprocal nature of gate-oxide capacitances in the BSIM4 MOSFET capacitance model [12].
First, we derive Z in by deriving Z o , Z in2 , and Z in1 in order.We note that, we use s and jω without differentiation since we are dealing with ac response only.
To derive Z o at the operating frequency, the series C o and R so in Figure 2 can be transformed to the parallel equivalents, C p and R p [11].Then Y o = 1/Z o is simply expressed as 1 1 1 where Figure 3 shows the ac equivalent circuit to derive an expression for Z in2 .Notice that, in the circuit shown in Figure 3, the non-reciprocal capacitance C sd2 is used instead of C ds2 , since we are looking into the source of M 2 .
By neglecting the parallel (C sg2 + C js2 ) branch, we derive the input admittance Y in21 first, and add s(C sg2 + C js2 ) to find Y in2 = 1/Z in2 .When the (C sg2 + C js2 ) branch is neglected, the circuit can be characterized by ( 2) and (3).
By eliminating v o in (2) and (3), we can express Y in21 as
Then Y in2 are expressed as Figure 4 shows the ac equivalent circuit to derive an expression for Z in1 .The circuit can be characterized by ( 6), (7), and (8).


where

Output Impedance
Z out derivation can be done similarly as the Z in derivation using the equivalent circuit in Figure 2 assuming R si input termination.We present the results only here.and 2 where , , and 1 .
Then Z out is expressed as

Power Gain
To derive the LNA voltage gain, the equivalent circuit in Figure 2 is simplified into the one shown in Figure 5, where the whole circuit is expressed as a 3-stage cascaded amplifier.Z in1 , Z in2 and Z o in Figure 5 are already derived in ( 9), ( 5) and (1), respectively.Notice that A 1 v g1 , gZ out2 , A 2 v s2 , and gZ out1 are the Thevenin equivalent voltages and impedances of the 2 nd and 3 rd gain stages in Figure 2. Therefore gZ out2 and gZ out1 differ from Z out2 and Z out1 in (11) and ( 12), respectively, and can be derived as follows.
By definition, gZ out2 corresponds to the impedance seen to the left of the v s2 node when v g1 = 0 in Figure 2, and can be derived using the equivalent circuit shown in Figure 6.
The circuit can be characterized by the Equations ( 14) and (15).
By eliminating v s1 in ( 14) and (15), gY out21 is expressed as Then gY out2 =1/gZ out2 is expressed as By definition, A 1 corresponds to the voltage gain v s2o /v g1 , where v s2o is the v s2 node voltage when open, and can be derived using the equivalent circuit shown in Figure 7.The circuit can be characterized by the Equations ( 18) and (19).  By eliminating v s1 in (18) and (19), we get where In Figure 2, the available input power P i , which is supplied to the LNA when impedance matched, is defined as 2 4 The maximum output power P o , which is supplied to the resistive load R so when impedance matched, is expressed as where v o and v out are defined in Figure 2, and R p is the transformed parallel resistance of R so , which is already defined relating (1).
Then the available power gain G is expressed as where A v1 , A v2 , and A v3 can be easily derived from Figure 5 as follows.

Automatic Sizing Algorithm
Figure 8 shows the automatic sizing algorithm developed in this work.The inputs to the algorithm include design and process specifications, and the outputs include synthesized design variable values are for R DB , W, nfb, L s , L g , C i , R 1 , L 1 , C o .Here, we explain the procedures from top to bottom in accordance with each step, which is explicitly indicated in Figure 8.  and process specifications.The design specifications include the operating frequency f, the input output terminations R si and R so , the supply current I DD , the desired power gain Gain_design.Instead of I DD , the power consumption PWR and the supply voltage V DD can be entered to calculate I DD by PWR/V DD .The process specifi-cations include the transistor channel length L, the transistor channel width per finger WF, and the maximum finger number nf_max defined for one unit of transistors.

2 nd Step: Calculation of Optimum Transistor Width
The next step is to calculate the transistor channel width W for optimum noise performance.The width for optimum noise performance is usually too large for practical use, and therefore the power-constrained noise optimization (PCNO) device width W optP [11] is adopted as W in this work.W optP is calculated according to the last rough equation in (29).
3 1 As shown in (29), W optP increases continuously as the frequency decreases.Therefore it may be necessary to define a maximum value for W considering lower frequency design.We suggest to limit W below 1000 μm.
If W F and nf_max are defined, the finger number nf is first calculated as W/W F , and the number of the maximum-fingered units m is calculated as the integer value of nf/nf_max, and the residual finger number nf_residue is determined as the residue to give an information for the transistor layout.Then the final W is determined by W = W F × (m × nf_max + nf_residue).We note that W F and nf_max are usually defined in most of recent processes.

3 rd Step: Calculation of Bias Circuit Design Variables and Getting DC Operating Point Information
The next step is to determine the bias circuit variable values and to get the dc operating point information.
The finger number for the bias transistor nfb and the drain bias resistance R DB in Figure 1 should be determined.By limiting the bias circuit current around 100 μA, for example, we can determine nfb by nfb = (100 μA/I DD ) × nf.For the decoupling resistor R B , we can simply use 5 kΩ, which is a reasonable value.
The next procedure is to determine R DB , which, however, is very difficult to determine by calculation.Since I DD is sensitive to the value of R DB , it should be manually determined to give the specified I DD value by dc circuit simulations.This procedure is one obstacle against full design automation in this work.However, it is an essential procedure since it provides the accurate operating point information to proceed with the remaining part of the design automation.The needed operating point information include the values of g m , g ds , C gs , C sg , C gd , C dg , C ds , C sd , C js , and C jd of M 1 and M 2 in Figure 1, which should be imported into the automatic sizing algorithm.

4 th Step: Iterations to Determine Design Variable Values
There are three main iteration loops in the automatic sizing algorithm as shown in Figure 8.The 1 st loop finds G max , which corresponds to the case with the upper limit of R 1 , which is chosen arbitrarily large enough as 10 kΩ in this work.To find G max , we need to find all the design variable values for the G max case simultaneously.Iteration is needed since the input and output matching designs affect each other.The 2 nd loop finds G min , which corresponds to the case with the lower limit of R 1 , which is arbitrarily chosen small as 40 Ω in this work to allow a larger allowable gain range.This iteration is also needed for the same reason explained for the G max case.The 3 rd loop finds the proper R 1 value for the desired gain Gain_ design by the bisection method, which lies within the lower and upper boundaries G min and G max , and its inner loop finds the corresponding design variable values for the present gain value during iteration similarly as in the 1 st and 2 nd iteration loops.

Iterations to Solve for the G max Case
As explained above, Z in1 is affected by output matching design, and Z out is affected by input matching design.Therefore we need some iteration to determine L s .Since Z in2 is affected by Z o , which is unknown yet, we need an initial guess for Z o to find the 1 st L s value.As shown in Figure 8, an initial guess for Z oL = Z o //(1/sC L ) is given as 50/g•m 2 , which is shown to be large enough for all possible situations in the procedure, to solve for Z in2 by (5).
The impedance seen at the gate of M 1 is equal to Z in1 , which is derived in (9).By setting the real part of Z in1 Re(Z in1 ) equal to R si for input impedance matching, we can find L s .However this equation Re(Z in1 ) = R si is too complicated to get the solution directly with the other present design variables values given, and therefore L s is solicited numerically within the lower and upper boundaries of 0.1 nH and 5 nH.We use the bisection method for this purpose.
The next procedure is to calculate L g and C i , which nullify the imaginary part of Z in1 Im(Z in1 ) in Figure 2. Z in1 is usually capacitive to give a negative value for Im(Z in1 ), and therefore L g can be calculated using the equation Im(Z in1 ) -1/(ωC i ) + ωL g = 0, where C i is simply a large dc blocking capacitor.We first calculate L g1 , which nullifies Im(Z in1 ) using Im(Z in1 ) + ωL g1 = 0.Although C i is larger the better, considering the layout size, 1/(ωC i ) = ωL g1 /10 is used to determine C i .L g is then recalculated using Im(Z in1 ) -1/(ωC i ) + ωL g = 0.
Depending on to the operating frequency and the desired gain, Z in1 may happen to be inductive, or this situation can happen in the middle of the iterations.For this case, a nominal single bond wire inductance of 1 nH is assumed for L g and Im(Z in1 ) -1/ωC i + ωL g = 0 is used to calculate the required C i value.
In the next procedure, the design variables L 1 and C o are determined using the equations Re(Z out ) = R so and Im(Z out ) = 0 for output impedance matching to R so , where Re(Z out ) is the real part of Z out expressed in (13).
If we let Z out1 in (12) equal to A + jB, the real and imaginary parts of Z out1 //jωL 1 in (13) are expressed as Then by letting Re(Z out ) = Re(Z out1 //jωL 1 ) = R so , L 1 is expressed as By letting Im(Z out ) = Im(Z out1 //jωL 1 ) -1/(ωC o ) = 0, C o is expressed as Using ( 31) and (32), L 1 and C o can be simply calculated.Now the 1 st set of the design variable values are ready to update Z oL and the remaining iterations are performed to find the final design variable values for the G max case.It was found that the iteration number for this loop should be larger than 10.
If the G max value is smaller than the desired gain, the routine gives a warning and stops.

Iterations to Solve for the G min Case
The 2 nd loop finds the design variable values for the G min case.The same iteration as above with the last Z oL value as an initial guess is performed to find G min using (25) again.

Iterations to Solve for the Gain_Design Case
The 3 rd loop finds the proper R 1 value for the desired gain Gain_design using the bisection method while the inner loop finds the corresponding design variable values for the present gain value.This inner iteration loop is exactly same as the 1 st and 2 nd loops.After all the design variables are determined for the present gain value, the gain is calculated using (25) again.If the calculated gain is equal to Gain_design within the allowed tolerance, the calculation stops to output the final set of the design variable values, which include W, nf, m, nf_residue, nfb, L s , L g , C i , R 1 , L 1 , and C o .

Verifications
The automatic sizing algorithm explained in Section 4 was coded using Matlab (Version 7.9.0.529) assuming usage of a 90 nm commercial CMOS process.The design variable sets for seven different operating frequencies ranging from 0.7 GHz to 5 GHz were synthesized, and verifications were done by one-time Spectre circuit simulations with the corresponding BSIM4.5.0 MOSFET model [12] for the assumed process.
The design specifications include I D = 5 mA, V DD = 1.2 V, Gain_design = 21 dB, and R si = R so = 50 Ω.The process specifications include L = 75 nm, W F = 3 μm, and nf_max = 64, where 75 nm for L is the effective channel length in this process.The maximum transistor width was set as W max = nf_max × m × W F = 64 × 5 × 3 μm = 960 μm, which is below 1000 μm as we suggested.
As examples of the verifications, Figures 9 and 10 show the simulated LNA characteristics without any tuning for the operating frequency of 1 GHz and 5 GHz, respectively, when the corresponding sets of the design variable values obtained using the automatic sizing algorithm are used for the simulations.The synthesized design variable values are as follows; Table 1 summarizes the simulated results of the seven designs, which reside in the frequency range, where the automatic sizing program could provide the design variable set for Gain_design of 21 dB.Notice that, for the operating frequencies below 1 GHz, the synthesized W values are restricted to below 960 μm, which is equal to the value for W max .
In Table 1, we can see that the input and output matchings (S 11 and S 22 ) are pretty good for all the designs, and the noise figure is pretty close to the noise figure minimum, which demonstrates the adequacy of the designs.
We note that power gain values are about the same with S 21 values.The S 21 values in Table 1 are smaller than the desired gain of 21 dB.This seems to be caused by neglecting g mb , C gb , R s , R d , R g , and R sub in the equivalent circuit in Figure 2. However we believe that the result is pretty good for the first-cut quick design.Table 2 summarizes the synthesized available gain ranges with the corresponding R 1 values for each design.We can see that a wide range of power gain can be obtained by varying the R 1 values as expected.

Conclusions
The analytical expressions for the principle parameters   were derived using the ac equivalent circuit of the singleended narrow-band cascode CMOS LNA adopting the inductive source degeneration.Based on the expressions, the automatic sizing algorithm was developed by adopting the power-constrained noise optimization criteria.The algorithm was coded using Matlab, and could provide a set of design variable values within seconds.One-time Spectre simulations without any tuning assuming usage of a commercial 90 nm CMOS process were performed to confirm that the automatic sizing program can synthesize the aimed first-cut design with a reasonable accuracy for the frequency range reaching up to 5GHz.This work showed in detail how the accurate automatic sizing can be done in an analytical approach.The approach can be applied to a common source LNA more easily since the derivation of principal parameters will be simpler with a fewer gain stages.It can be also applied to a differential LNA easily since the derivation will be basically same.The approach seems applicable to more complicated designs even though the derivation procedures will contain enhanced complexity.
The automatic sizing program may be utilized efficiently for additional tuning purpose.For example, after

Figure 5 .
Figure 5. Equivalent circuit to find the voltage gain.
process specifications calculation of W optP ; WoptP , nf , m, nf_ residue calculation of nf for bias ckt ; nfb circuit sim ulation to get the D C operating point for the given pow er consum ption im porting the D C operating point inform ations iniInitial guess for Z oL to cal culate Gm ax(R 1= 10 kO) Find Ls for the Gm ax (R 1= 10 kO) case using bisection m ethod ; Ls = 0. 1 ~5 nH calculation of Lg & C i calculation of Zout w ith R si =50 O calculation of L 1 & C o for output 50 O m atching re-calculation of ZoL repeat k tim es for Gm ax case calculation of Gm ax ; Value _ g_ r= Gm ax-gain _design If gian _ desi give a w gn > Gm ax , arning !Find Ls for the Gm in (R 1= 40 O) case using bisection m ethod ; Ls = 0 .1 ~3 nH calculation of Lg , C i, L 1, C o, Zp calculation of Gm in ; Value _g_ l = Gm in -Gain _design find Ls for each R 1 case during R 1 iteration ; Ls = 0 .1 ~3 nH If value _ g_ l
A 2 corresponds to the voltage gain v oo /v s2 , where v oo is the v o node voltage when open, and A 2 derivation can be done in the similar fashion to the one for A 1 derivation.The resulting A 2 is expressed as

Table 2 . Synthesis summary for the available gain ranges with the corresponding R 1 values.
f [GHz] W [μm] S 21 [dB] R 1 [Ω]