An Enhanced Bulk-Driven Folded-Cascode Amplifier in 0 . 18 μ m CMOS Technology

A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50 ̊C to 100 ̊C.


Introduction
Design of high-performance integrated circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages, especially in analog part.This requires traditional analog circuit solutions to be replaced by new approaches to get the best performance and more flexible mixed-mode structure strategies that are compatible with future standard CMOS technology trends.This combination of the analog and digital parts should be done in an optimal way and the optimization process is application dependent [1][2][3][4].The main bottleneck in analog circuits is the operational amplifier.Meanwhile, fully differential amplifiers have better performance compared to the single ended amplifiers.The single-stage amplifiers are inherently less prone to instability; most applications use the amplifier in a closedloop feedback configuration which can result in instability.This possible instability is likely to manifest under high frequency operation.However, single-stage amplifiers suffer of lower voltage gain compare to the multistage amplifiers, especially in low-voltage applications and future deep sub-micron technologies.However multistage amplifiers introduce more low frequency poles and available compensation techniques limit the amplifier's speed; nevertheless, they consume much more power.On the other hand, achieving high gain/swing performance is hardly possible for single-stage amplifiers [5].
Fully differential folded-cascode (FC) amplifier is being used in many low-voltage and high bandwidth applications and does not suffer from "mirror pole" limitations.This structure is utilized in many cases and exhibits a superior performance because of its special features like potentially high gain, single parasitic pole, wide bandwidth, acceptable limitation of the common mode (CM) voltage range [5][6][7][8].Besides, bulk-driven (BD) amplifiers or complex gain enhancement techniques are other techniques that have been already introduced to boost the voltage gain of amplifiers.Recently, a number of techniques for increase in the gain of BD amplifiers have been reported [9][10][11]; but for a sufficient gain, most of them utilize multi-stage or gain-boosting structures.This paper presents the design of a modified structure of single-stage BDFC amplifier that has significant performance in comparison with the conventional BDFC amplifier.It is shown that the proposed amplifier has higher DC-Gain, without degrading of the frequency and transient responses, due to the action of the new merge circuit topology.The proposed structure is done in 0.18 µm triple-well CMOS process for switched-capacitor applications.The design procedures of this paper are organized as follows.Section 2 analyses the small signal of conventional and proposed BDFC amplifiers and introduce the bias and common-mode feedback (CMFB) structures.Section 3 presents the simulation results.Finally the conclusion is given in Section 4.

Conventional Bulk-Driven Folded-Cascode Amplifier
A typical PMOS BDFC amplifier in differential mode capable of operating with low supply voltage is depicted in Figure 1.Because of high performance and wide applications, the detailed analysis of this structure has been explained in [5,6].NMOS and PMOS transistors ac currents are derived by: where g m , g mb , and g ds are gate transconductance, bulk transconductance, and output conductance, respectively.By using Equations ( 1) and ( 2) and considering  , the differential DC-Gain of corresponding amplifier is calculated by: By applying good approximations, the differential DC-Gain of this amplifier is calculated as: In a typical 0.18 µm CMOS process, a voltage gain about of 39 dB and unity gain bandwidth (UGBW) of approximately 14.5 MHz with phase margin of 89.7˚ for a capacitive load of 1pF is achievable (bias current of branches is 40 µA).To increase the DC-Gain of conven-tional FC amplifier, a new technique is proposed in Section B.

Proposed Structure
The To achieve high DC-Gain in amplifier, the bulk terminals of transistors M 5 to M 8 is used in new configuretion, which NMOS and PMOS devices are in opposite phases.These transistors are auxiliary transistors which increases the output resistance, so DC-Gain will boost.Figure 2 shows the proposed amplifier without bias and CMFB circuits.Using Kirchhoff's Current Law at the node  , the KCL Equation becomes: therefore, using Equations ( 1) and ( 2), result in: , and also using Equations ( 1) and ( 2     substituting (11) to ( 13) into ( 7) results in: m ds ds m ds ds g r g r r r g r r g r g r r r It is clear that with increasing the 1 K and 2 K , the output resistance will be boosted.A significant enhancement in the total value of A is obtained conesquently.Indeed 1 K will be controlled by choosing appropriate biases and sizes of M 5 to M 8 , especially controlling the bulk terminals of 1 and 2 V of these transistors.However, 5 9 mb ds V g r must be greater than 1, because excluding it might take 1 K to zero and decrease the DC-Gain, so before fabrication, the proposed amplifier must be simulated in the corners of fabrication process and wide temperature ranges.In this design procedure, 1 1.33 K  and 2 9.12 K  are obtained, respecttively.Bias circuit and CMFB block which utilized in the conventional and proposed structures is shown in

Simulation Results
In this section, simulation results of the proposed amplifier are shown and are compared with the conventional structure.Amplifiers have been designed in a typical 0.18 µm CMOS process with the same capacitor load and power consumption and then simulated by HSPICE environment using level 49 parameters.A closed-loop configuration with 1 pF capacitors is used to study the linearity and step response of the amplifiers, which is shown in Figure 5.With the mentioned value of capacitors, closed-loop gain of the amplifiers is approximately 0 dB.HSPICE AC simulation results of the proposed and the conventional FC amplifiers are shown in Figure 6.The UGBW and phase margin of both structures are approximately equal.As demonstrated in Figure 6, the proposed amplifier achieves a DC-Gain about 50 dB which is 11 dB higher than DC-Gain of the conventional amplifier in the same power supply and process.It is considerable that by choosing a greater amount of both 1 K and 2 K in Equation ( 16) higher DC-Gain can be achieved.Total Harmonic Distortion (THD) of both amplifiers for input CM voltage up to 1.2 Vp-p was tested.For 50 KHz and 1.2 Vp-p input frequency, THD of conventional and proposed structures were -37.97 dB and -42.2 dB, respectively.output voltage amplitudes.However, in higher output voltage amplitudes, both amplifiers have acceptable linearity and eliminate undesirable harmonics.The accuracy of the amplifiers for different input step voltage amplitudes in unity gain configuration was also tested.The result of the step response simulation for 500 mV amplitude is illustrated in Figure 8, which demonstrate that the accuracy of the proposed amplifier is more than 8 bit for up to 500 mV output voltage swing.Figure 9 illustrates the effective input transconductance of amplifiers as a function of the input CM voltage.It is obvious that both designs function correctly for rail-torail input CM voltage values with acceptable variations.Finally, the simulated performance of both amplifiers and its comparison with previous structures are summarized in Table 1.In order to compare the relative performance of structures, a new figure of merit (FOM) is used as follows: -UGBW FOM 20 log

Conclusions
In this paper, a novel approach to increase the DC-Gain of conventional BDFC amplifier is presented.With the presented method the DC-Gain of proposed amplifier increased more than 11 dB.All transistors in both amplifiers have same size and both designs consume 375 µW with 1 pF capacitive load.
Accuracy in the closed-loop configuration of amplifier in higher output voltage swings is the main advantage of the proposed structure.Step response simulations demonstrate that the accuracy of the proposed amplifier is more than 8 bit for up to 500 mV output voltages swing.Moreover, THD simulations show that proposed amplifier achieves reasonable linearity in comparison with conventional structure in different voltage swings, especially in large input signal swing.
to(10), Equations are obtained as follows:

Figure 7 .
Figure 7. THD comparison of amplifiers in different voltage swing.

Figure 9 .
Figure 9. Effective bulk-transconductance of amplifiers from rail-to-rail.The unit of proposed FOM is   MHz pF mV mW   , which this form the benchmark for the comparison with the results from this work.