A High-Speed DLL-Based Hybrid Phase Conjugator for 5G Beamforming

A delay-locked loop based hybrid phase conjugator (DLL-HPC) is presented as a possible solution for 5G beamforming. Theoretical background, unique capabilities, and experimental verification are presented. The proposed DLL-HPC provides backwards compatibility with existing beamforming protocols as well as sub-millisecond beamsteering and automatic mobile target tracking with zero communication overhead. A proof-of-concept DLL-HPC prototype has been constructed from commercially available components to operate in the 5G NR-FR1 band, indicating that the technique can be readily adopted with available technology.


Introduction
Advanced beamforming techniques have been identified as a key enabling technology for coming Millimeter Wave (mmWave) 5G communications [1] [2] [3] [4] [5]. As carrier frequencies rise into the K and K a bands, individual antenna element sizes shrink and make extremely narrow, highly directional beams easier to produce [2] [6] [7] [8] [9]. The gain provided by these pencil beams will be necessary to overcome the high path-loss of mmWave frequencies as well as to reduce the amount of interference among the many users [1] [6] [7] [10] [11] [12]. mmWave 5G communications are intended to enable multi-gigabit throughput among many dynamic users within a small area, meaning that new beamforming technologies must not only establish a strong physical link but also continually update it to track moving targets [1] [2] [5] [6] [7] [8] [13].
Many current beamforming techniques, such as those implemented in IEEE 802.11 ad/ay, have high costs associated with them [1]. They rely exclusively on the transmission of beamformer training information between users and can require many communication frames to establish a strong connection, raising communication overhead and reducing throughput [1] [6] [10]. Additionally, these methods only reevaluate the current point if the communication link degrades, making them unsuited for dynamic environments with mobile users [1] [8]. Furthermore, the utilization of pencil beams in mmWave 5G communications could lead to frequent beam switching and deafness when misaligned, owing to a tradeoff between beamwidth and data throughput [4] [7] [10] [13].
A promising solution for establishing and maintaining strong communication links is the retrodirective array (RDA), an antenna array constructed of phase conjugators which transmits back along the direction of arrival (DoA) of a received signal [14] [15] [16]. A phase conjugator design capable of being reconfigured as an actively controlled phase shifter could mitigate the shortcomings of existing retrodirective arrays, such as vulnerability to received signal dropout and a lack of backwards compatibility with existing protocols, while still providing automatic mobile target tracking and lock-on without a priori knowledge of the signal's DoA [15] [17] [18]. This work presents a new delay-locked loop based hybrid phase conjugator (DLL-HPC) with rapid settling time, backwards compatibility with existing protocols, received signal dropout immunity, and DoA reporting capabilities. The proposed DLL-HPC is modular in nature, can be used to construct arbitrarily sized and shaped antenna arrays, and is a promising new technology for 5G systems. This paper is organized as follows. Section 2 details the theory of operation for the DLL-HPC and its functionalities. Section 3 outlines DLL-HPC unique capabilities. Section 4 presents experimental verification from a fabricated 5G NR-FR1 DLL-HPC prototype. Finally, conclusions are drawn and possible applications are outlined in Section 5.

Theory of Operation
The proposed DLL-HPC system is shown in Figure 1. It is important to note that this system is designed as a hybrid analog/digital system in order to leverage the advantages of each; these are most easily seen in the n th downconversion chain's feedback path. The DLL-HPC provides the option to choose between controlling the phase of the   19] [20] [21].
In order for the DLL-HPC to function as a phase conjugator, the microcontroller present in the downconversion chain's feedback path controls the generated carrier signal's phase through DAC n,2 . Additionally, all downconversion and carrier generation chains must be frequency synchronized; this can be achieved by using a common reference signal for all local oscillators (LO). With all signal chains frequency synchronized, the phases and frequencies relative to the 0 th , or reference, downconversion chain can be defined as shown in Table 1.

Received Signal Beamforming
By using a high-side LO and an appropriately designed IF filter and amplifier, the IF signal frequency will be: From Equation (2), the phase difference between the n th and reference IF signals can be written as: 0˚ can be substituted for θ 0 because the reference downconversion chain contains no controllable phase delay element, and the lo φ terms can be removed in favor of a i ∆ term. This new term encompasses any phase differences between the IF signals that are a product of the physical system: such as signal routing and the phase difference between the various LOs. Because all downconversion and carrier generation chains are frequency synchronized, this Δi term is a constant that depends only on the physical system. The final equation for the phase difference between the n th and reference IF signals is now: In steady-state operation the DLL will drive the downconversion chain phase delay n θ so that the IF signals will be in phase, or 20]. In this state the IF signals can be summed to provide maximal beamforming gain [22]. Alternatively, n θ can be controlled directly using ,1 n DAC to allow traditional active beamforming techniques to be used. As the Δ n i term is a constant, it can be calibrated out by a fixed offset when performing active beamforming.

Transmitted Signal Beamforming
By using frequency synchronized LO sources for the transmitted carrier signal generation chains, it can be seen from Figure 1 that: And further: A similar approach to defining the phase difference between IF signals can be adopted for the phase difference between the n th and reference generated carrier signals. Frequency synchronization allows a Δj term to be defined that encompasses the constant phase differences caused by the LOs and signal routing to arrive at: , Because the n j ∆ term is constant and depends only on the physical system, it can be calibrated out with a fixed offset stored in the microcontroller's memory.

Phase Conjugation
The criteria for phase conjugation of a received signal states that the transmitted signal's phase must be the negative of the received signal's phase, or . Phase conjugation allows RDAs to transmit a signal back along the received DoA without a priori knowledge [14] [15] [18].
The DLL-HPC achieves quick phase conjugation through the use of look-up tables (LUTs) and well-characterized phase delay blocks. By monitoring the downconversion chain's phase delay control signal while the DLL-HPC is in steadystate, a LUT can be used to determine what the current value of n θ is at that given time. With this knowledge, it is a simple matter to set n n ξ θ = − through a second LUT to achieve phase conjugation. As the settling time of a DLL is extremely fast, the limiting factor of the speed of the DLL-HPC is the sampling rate of the microcontroller's analog-digital and digital-analog converters [21].
In order to remove the Δ n i and Δ n j terms in Equation (4) and Equation (7), a simple calibration procedure can be performed. In-phase signals can be applied to the DLL-HPC receiver so that

DLL-HPC Unique Capabilities
The DLL-HPC maintains the core advantages of a traditional RDA, namely the ability to track moving targets and accurately transmit back along the DoA of a received signal in dynamic environments [15] [17]. Additionally, the presence of a digital control element in the DLL-HPC allows for the following extra functionalities:

Backwards Compatibility with Beamforming Protocols
The DLL-HPC's separation of downconversion and carrier signal generation chains and ability to be reconfigured as an actively steered phase shifter allow for backwards compatibility with previous beamforming protocols, such as those outlined in IEEE 802.11 ad/ay [1].

Direction of Arrival Reporting
Phase-locked loop and mixer-based RDAs have no way of reporting the phase of the received carrier signal [15] [24]. Because the DLL-HPC's digital control element measures and conjugates the received signal phase directly, it is also able to record and report the received signal phase with little overhead. If the array geometry is known, this allows for real-time DoA monitoring and system environment analysis. If this information is shared among members of a network, a Spatial Division Multiple Access (SDMA) scheme can be used to allow for context-aware reuse of frequency bands as illustrated in Figure 2.

Received Signal Dropout Immunity
The DLL-HPC's ability to track and store the DoA of a received carrier signal can be used to prevent system decoherence in the case of received signal dro-

Initial Acquisition Scheme
The proposed DLL-HPC architecture would enable a new suite of beamforming techniques if adopted in a large-scale communication system. The greatest performance improvement would be seen in acquiring and maintaining beamformer patterns over the current standards [1]. Instead of reducing system throughput by continually reevaluating and retransmitting beamformer training information [1] [3], a point between two transceivers could be established quickly and with no continual communications overhead.
A possible methodology involves two transceivers switching between actively controlled and retrodirective modes as illustrated in Figure 3. Alternatively, a low-power beacon signal could be transmitted from base stations to allow users to automatically identify the DoA and beamform accordingly.

Experimental Results
In order to verify the operation and versatility of the proposed DLL-HPC system architecture, a proof-of-concept prototype was fabricated using only commercially available off-the-shelf components to operate at 5G NR-FR1 frequencies from 2.100 GHz to 2.600 GHz. The fabricated prototype operates with an IF frequency of 10 MHz and is capable of performing phase conjugation and beamforming of any combination of receive/transmit carrier frequencies within the 5G NR-FR1 band. A phase-frequency detector (PFD) and charge pump were chosen as feedback in the DLL portion of the design due to their fast settling times and 0˚ steady-state error. Measurements were made using a Tektronix MSO64 oscilloscope, and a Keysight M8196A Arbitrary Waveform Generator (AWG) was used to generate phase-shifted sources for testing. The fabricated prototype system consumed 2.42 W of power in steady-state operation. Components used in the prototype design are listed in Table 2.

Direction of Arrival Reporting
DoA reporting capabilities were verified by recording the DLL-HPC's reported received signal phase and comparing it to the actual phase generated by the AWG. The DLL-HPC prototype was able to report the received signal phase with an average error magnitude of 2.59˚ and an average error of +1.0˚. As this proof-of-concept prototype consisted of only a single DLL-HPC, no array-level DoA calculations can be shown at this time.

Settling Time and Dynamic Phase Tracking
The settling time of the DLL-HPC was found by recording the control signals for each phase delay block when a step change occurred in the received signal phase. In order to further verify the ability of the DLL-HPC to actively track mobile targets, the relative phase difference of the received signal was swept linearly from 0˚ to 360˚ to 0˚ in a cycle with various rates of change from 50˚/s to 15,000˚/s. In each test, the DLL-HPC's closed-loop received signal chain was able to accurately track the changing phase as shown in Figure 5. The transmitted signal beamformer portion of the DLL-HPC was not characterized in these tests, its settling time is limited by the ADC and DAC sampling rates of the prototype; however, sufficiently high sampling rates will allow the same transmitted signal beamformer tracking rates.

Conclusions
A novel DLL-based Hybrid Phase Conjugator architecture has been proposed alongside experimental verification. The proposed DLL-HPC has been shown to be capable of performing phase conjugation with small errors and rapid settling times. This system provides a unique combination of features that no other RDA or beamforming circuit/protocol is able to duplicate: retrodirection capability, active steering capability, rapid settling time, small phase errors, received signal dropout immunity, DoA reporting, automatic mobile target tracking, and back- The characterization and simulation of DLL-HPC based antenna arrays in environments characteristic of mmWave 5G applications is currently underway, and results will be reported in a timely manner.

Funding
This work was supported by FiWIN grant NSF-IIP-1822055.