Circuits and Systems

Vol.2 No.4(2011), Paper ID 7906, 8 pages

DOI:10.4236/cs.2011.24050

 

Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

 

Chin-Hsin Lin, Marek Syrzycki

 

 

Copyright © 2011 Chin-Hsin Lin, Marek Syrzycki et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


C. Lin and M. Syrzycki, "Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution," Circuits and Systems, Vol. 2 No. 4, 2011, pp. 365-371. doi: 10.4236/cs.2011.24050.

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