Circuits and Systems

Vol.7 No.13(2016), Paper ID 72096, 17 pages

DOI:10.4236/cs.2016.713343

 

A Modified PFD Based PLL with Frequency Dividers in 0.18-µm CMOS Technology

 

N. K. Anushkannan, H. Mangalam

 

Department of Electronics and Communication Engineering, Tamil Nadu College of Engineering, Coimbatore, India
Department of Electronics and Communication Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India

 

Copyright © 2016 N. K. Anushkannan, H. Mangalam et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article

Anushkannan, N. and Mangalam, H. (2016) A Modified PFD Based PLL with Frequency Dividers in 0.18-µm CMOS Technology. Circuits and Systems, 7, 4169-4185. doi: 10.4236/cs.2016.713343.
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