Circuits and Systems

Vol.7 No.12(2016), Paper ID 71686, 12 pages

DOI:10.4236/cs.2016.712333

 

Area Efficient Sparse Modulo 2n - 3 Adder

 

Ritesh Kumar Jaiswal, Chatla Naveen Kumar, Ram Awadh Mishra

 

Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India

 

Copyright © 2016 Ritesh Kumar Jaiswal, Chatla Naveen Kumar, Ram Awadh Mishra et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Jaiswal, R. , Kumar, C. and Mishra, R. (2016) Area Efficient Sparse Modulo 2n - 3 Adder. Circuits and Systems, 7, 4024-4035. doi: 10.4236/cs.2016.712333.

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