International Journal of Communications, Network and System Sciences

Vol.2 No.6(2009), Paper ID 702, 8 pages

DOI:10.4236/ijcns.2009.26064

 

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

 

C. ARUN, V. RAJAMANI

 

 

Copyright © 2009 C. ARUN, V. RAJAMANI et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


C. ARUN and V. RAJAMANI, "A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering," International Journal of Communications, Network and System Sciences, Vol. 2 No. 6, 2009, pp. 575-582. doi: 10.4236/ijcns.2009.26064.

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