Circuits and Systems

Vol.7 No.8(2016), Paper ID 67240, 8 pages

DOI:10.4236/cs.2016.78119

 

A New Clock Gated Flip Flop for Pipelining Architecture

 

Krishnamoorthy Raja, Siddhan Saravanan

 

Excel Engineering College, Komarapalayam, India
Muthayammal Engineering College, Rasipuram, India

 

Copyright © 2016 Krishnamoorthy Raja, Siddhan Saravanan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article

Raja, K. and Saravanan, S. (2016) A New Clock Gated Flip Flop for Pipelining Architecture. Circuits and Systems, 7, 1361-1368. doi: 10.4236/cs.2016.78119.
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