Circuits and Systems

Vol.7 No.6(2016), Paper ID 66356, 13 pages

DOI:10.4236/cs.2016.76054

 

Design and Implementation of Efficient Reversible Arithmetic and Logic Unit

 

Subramanian Saravanan, Ila Vennila, Sudha Mohanram

 

Department of EEE, P. S. G. College of Technology, Coimbatore, India
Department of EEE, P. S. G. College of Technology, Coimbatore, India
Sri Eshwar College of Engineering, Kondampatty, Coimbatore, India

 

Copyright © 2016 Subramanian Saravanan, Ila Vennila, Sudha Mohanram et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Saravanan, S. , Vennila, I. and Mohanram, S. (2016) Design and Implementation of Efficient Reversible Arithmetic and Logic Unit. Circuits and Systems, 7, 630-642. doi: 10.4236/cs.2016.76054.

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