Department of ECE, KCG College of Technology, KCG Nagar, Chennai, India
Department of ECE, College of Engineering, Guindy, Anna University, Chennai, India
Department of ECE, College of Engineering, Guindy, Anna University, Chennai, India
Copyright © 2016 Dr. Deepa Jose, P. Suganya, Dr. Palanichamy Nirmal Kumar et al. This is
an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any
medium, provided the original work is properly cited.
How to Cite this Article
Jose, D. , Suganya, P. and Kumar, D. (2016) Content Addressable Memory Using Automatic Charge Balancing with Self-Control Mechanism and Master-Slave Match Line Design.
Circuits and Systems,
7, 597-611. doi:
10.4236/cs.2016.76051.