Circuits and Systems

Vol.7 No.4(2016), Paper ID 66002, 11 pages

DOI:10.4236/cs.2016.74029

 

Design of Efficient Router with Low Power and Low Latency for Network on Chip

 

M. Deivakani, D. Shanthi

 

Department of Electronics and Communication Engineering PSNA College of Engineering and Technology, Dindigul, India
Department of Computer Science Engineering PSNA College of Engineering and Technology, Dindigul, India

 

Copyright © 2016 M. Deivakani, D. Shanthi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article

Deivakani, M. and Shanthi, D. (2016) Design of Efficient Router with Low Power and Low Latency for Network on Chip. Circuits and Systems, 7, 339-349. doi: 10.4236/cs.2016.74029.
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