Circuits and Systems

Vol.6 No.12(2015), Paper ID 62409, 12 pages

DOI:10.4236/cs.2015.612028

 

An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS

 

Ananthanarayanan Parthasarathy

 

Department of Electrical Engineering, Stanford University, Stanford, USA

 

Copyright © 2015 Ananthanarayanan Parthasarathy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Parthasarathy, A. (2015) An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS. Circuits and Systems, 6, 280-291. doi: 10.4236/cs.2015.612028.

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