Graduate School of Engineering, Osaka University, Osaka, Japan
Graduate School of Engineering, Osaka University, Osaka, Japan
Graduate School of Engineering, Osaka University, Osaka, Japan
Faculty of Engineering, Osaka Institute of Technology, Osaka, Japan
Graduate School of Engineering, Osaka University, Osaka, Japan
Copyright © 2015 Jungnam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Takao Kihara, Toshimasa Matsuoka et al. This is
an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any
medium, provided the original work is properly cited.
How to Cite this Article
Bae, J. , Radhapuram, S. , Jo, I. , Kihara, T. and Matsuoka, T. (2015) A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing.
Circuits and Systems,
6, 136-142. doi:
10.4236/cs.2015.65014.