Circuits and Systems

Vol.6 No.3(2015), Paper ID 55133, 10 pages

DOI:10.4236/cs.2015.63009

 

Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers

 

Nivedita Jaiswal, Radheshyam Gamad

 

Department of Electronics and Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, India
Department of Electronics and Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, India

 

Copyright © 2015 Nivedita Jaiswal, Radheshyam Gamad et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Jaiswal, N. and Gamad, R. (2015) Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers. Circuits and Systems, 6, 81-92. doi: 10.4236/cs.2015.63009.

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