Circuits and Systems

Vol.6 No.3(2015), Paper ID 54988, 10 pages

DOI:10.4236/cs.2015.63007

 

Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits

 

Ashok Babu Ch, J. V. R. Ravindra, K. Lalkishore

 

Department of Electronics and Communication Engineering, SVIT, Sec-Bad, India
Department of Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad, India
Jawaharalal Nehru Technological University, Anantapur, India

 

Copyright © 2015 Ashok Babu Ch, J. V. R. Ravindra, K. Lalkishore et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Ch, A. , Ravindra, J. and Lalkishore, K. (2015) Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits. Circuits and Systems, 6, 60-69. doi: 10.4236/cs.2015.63007.

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