Circuits and Systems

Vol.4 No.3(2013), Paper ID 33699, 4 pages

DOI:10.4236/cs.2013.43037

 

Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

 

Omnia S. Ahmed, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, Hassanein H. Amer, Ahmed H. Madian

 

Faculty of Engineering, Cairo University, Giza, Egypt
Faculty of Engineering, Cairo University, Giza, Egypt
College of Computing and Information Technology, Arab Academy for Science, Technology & Maritime Transport, Cairo, Egypt
Electronics Engineering Department, American University in Cairo, Cairo, Egypt
Radiation Engineering Department, Egyptian Atomic Energy Authority, Cairo, Egypt

 

Copyright © 2013 Omnia S. Ahmed, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, Hassanein H. Amer, Ahmed H. Madian et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Ahmed, O. , Abu-Elyazeed, M. , Abdelhalim, M. , Amer, H. and Madian, A. (2013) Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits. Circuits and Systems, 4, 276-279. doi: 10.4236/cs.2013.43037.

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