Circuits and Systems
Vol.3 No.3(2012), Paper ID 20205, 10
pages
DOI:10.4236/cs.2012.33034
Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration
Hiroshi Makino, Naoya Okada, Tetsuya Matsumura, Koji Nii, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Faculty of Information Science and Technology, Osaka Institute of Technology, Hirakata, Japan
Graduate School of Natural Science, Kanazawa University, Kanazawa, Japan
SoC Software Platform Division, Renesas Electronics Corporation, Itami, Japan
Design Platform Development Division, Renesas Electronics Corporation, Kodaira, Japan
Faculty of Engineering, Osaka Institute of Technology, Osaka, Japan
Faculty of Information Science and Technology, Osaka Institute of Technology, Hirakata, Japan
Graduate School of Natural Science, Kanazawa University, Kanazawa, Japan
Copyright © 2012 Hiroshi Makino, Naoya Okada, Tetsuya Matsumura, Koji Nii, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda et al. This is
an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any
medium, provided the original work is properly cited.
How to Cite this Article
H. Makino, N. Okada, T. Matsumura, K. Nii, T. Yoshimura, S. Iwade and Y. Matsuda, "Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration,"
Circuits and Systems, Vol. 3 No. 3, 2012, pp. 242-251. doi:
10.4236/cs.2012.33034.