ABSTRACT

An open source high level synthesis fixed-to-floating and floating-to-fixed conversion tool is presented for embedded design, communication systems, and signal processing applications. Many systems use a fixed point number system. Fixed point numbers often need to be converted to floating point numbers for higher accuracy, dynamic range, fixed-length transmission limitations or end user requirements. A similar conversion system is needed to convert floating point numbers to fixed point numbers due to the advantages that fixed point numbers offer when compared with floating point number systems, such as compact hardware, reduced verification time and design effort. The latest embedded and SoC designs use both number systems together to improve accuracy or reduce required hardware in the same design. The proposed open source design and verification tool converts fixed point numbers to floating point numbers, and floating point numbers to fixed point numbers using the IEEE-754 floating point number standard. This open source design tool generates HDL code and its test bench that can be implemented in FPGA and VLSI systems. The design can be compiled and simulated using open source Iverilog/GTKWave and verified using Octave. A high level synthesis tool and GUI are designed using C#. The proposed design tool can increase productivity by reducing the design and verification time, as well as reduce the development cost due to the open source nature of the design tool. The proposed design tool can be used as a standalone block generator or implemented into current designs to improve range, accuracy, and reduce the development cost. The generated design has been implemented on Xilinx FPGAs.

Keywords:

FPGA, VLSI, RTL, Iverilog, GTKWave, OCTAVE, HLS, C#, Open Source

1. Introduction

Most embedded systems, System-on-Chip (SoC) and transmission systems are implemented using either fixed point, floating point or hybrid number systems wherein fixed [1] [2] and floating point numbers [3] [4] can be used together in the same chip [5] - [7] . The IEEE754-1985 standard was released for binary floating point arithmetic with some new features such as better precision, range and accuracy [8] . The current standard includes half precision, single, double, double-extended and quadruple precisions [8] .

The single precision binary 32-bit floating and 32-bit fixed point numbers are shown in Figure 1. The most significant bit (index number 31) of the floating point number is the sign bit. The next eight bits are biased exponents (index numbers 30 - 23) and the last 23 bits are fraction bits [8] - [10] . The representation and decimal calculation of the single precision floating-point number are shown in Equations (1) and (2), respectively:

(1)

(2)

The 32-bit fixed point number that is shown in Figure 1 has an integer signed-fixed point number and its decimal equivalent is shown in Equations (3) and (4), respectively:

(3)

(4)

The numbers that are used in many DSP and communication systems are scaled between [−1, 1). The [−1, 1) scaled version of equations (3) and (4) can be written as Equations (5) and (6) respectively:

(5)

(6)

The hardware implementation of fixed point number systems requires less hardware than floating point number systems. The implementation of addition in a floating point number system can be particularly difficult and will consume more hardware than fixed point numbers. Fixed point numbers are limited to the number of bits used as shown in Figure 1. For example, representing the current U.S. National debt, which is 19,246,968,550,852 dollars [11] , requires 45-bit fixed point number system. Representing the same debt in Mexican pesos, which is 337,858,398,896,373, requires a 49-bit fixed-point number system, and 44,385,703,632 bit coins require a 36-bit fixed point number system. These numbers can be represented using single precision 32-bit floating numbers 0 × 558C0A46, 0 × 5799A3E5, and 0 × 51255981, respectively. Another advantage of a floating-point number system is in the representation of smaller numbers [9] . For example, the charge and mass of a proton are 1.60217646 × 10⁻¹⁹C and 1.6726219 × 10⁻²⁷ kg, which can be represented as 32-bit floating point numbers as 0 × 203D26D0 and 0 × 130484CD, respectively. The error during this representation is 3.9999 × 10⁻²⁷. To represent the charge of a proton using a fixed-point number system [12] , an 80-bit is required. Error during this representation is 6.5653 × 10⁻²⁵. To reduce this error, the number of bits needs to be increased to 88-bit. This error is reduced to 3.4346 × 10⁻²⁵. This shows that floating point numbers offer better dynamic range.

To improve design accuracy, improve range and reduce design time and cost, a custom fixed-to-floating and floating-to-fixed-point conversion tool is proposed. This conversion tool is described in Section 2. FPGA implementation and results are discussed in Section 3, and the conclusion and future work are given in Section 4.

2. Fixed-to-Floating Point Conversion System

Most hardware blocks in the latest processors, microcontrollers, microprocessors, and many special purpose arithmetic logic units (ALU) use fixed and floating point arithmetic operations. Some of these hardware blocks need to communicate with each other or I/O needs to be represented in either fixed and/or floating point numbers. Fixed-to- floating and floating-to-fixed point conversion blocks are often needed to properly transfer the data as seen in Figure 2 below. Designing and verifying these blocks could be time consuming and require a longer time-to-market (TTM) cycle.

The proposed conversion tool shown in Figure 3 can accelerate TTM [13] by reduc-

ing the verification time if IEEE-754 floating point or custom floating point arithmetic are required. The GUI of the proposed the conversion system is developed in C# with Window Presentation Foundation (WPF). The developed software is inherently executable in every Windows PC running Windows 7 or greater. The software does not require any special runtime except .NET, which is available in every Windows PC. The GUI incorporates the Model-View-View Model (MVVM) model for improved interaction and easy user interface. It is modular, refactorable and easily extendable. The GUI code and the logic are separated via MVVM model so that developing UI does not interfere with the main aspect of the software.

This conversion tool takes an n-bit fixed point input and creates a 32-bit floating point number and also takes a 32-bit floating point number and creates an n-bit fixed point output. This tool creates IEEE 754-based hardware and test bench using Verilog HDL. The test bench is created using C# and functional verification is done using Iverilog [14] , GTKWave [15] and OCTAVE [16] . This code is also checked using LEDA [17] for ASIC and FPGA compatibility. The components of this conversion system are:

Ÿ Float-to-Fixed: This is an optional check box to generate a float-to-fixed conversion block. The system converts a 32-bit single precision floating point number to any n-bit fixed point number.

o Fixed Point Total Bits: This is a user defined field for fixed point number n. The current system supports any value of n. The default value for this field is 32 bits.

o Total Test Vectors Generate: This is a user defined field for the number of test vectors. The current system supports any value of the test vectors. The default value for this field is 100.

Ÿ Fixed-to-Float: This is an optional check box to generate fixed-to-float conversion block. The system converts any n-bit fixed point number to a 32-bit single precision floating point number.

o Fixed Point Total Bits: This is a user defined field for fixed point number n. The current system supports any value of n. The default value for this field is 32 bits.

o Total Test Vectors Generate: This is a user defined field for the number of test vectors. The current system supports any value of test vectors. The default value for this field is 100.

Ÿ Select Iverilog Directory: This design and verification software supports both Iverilog and Modelsim compilers and simulators. Due to the open source nature of the software, only Iverilog verification is performed. The generated RTL code can be compiled and simulated using third party EDA tools if necessary. The correct Iverilog path needs to be entered for proper verification operation. The default of Iverilog installation path is used as default for the design tool.

Ÿ Generate Octave File for Error Analysis: During Iverilog verification process values are compared using the expected values and error is displayed in a plot window. This method is an easy way to verify a large amount of test vectors.

The idea behind the fixed-to-floating point conversion system is similar to the High Level Synthesis (HLS) [18] design flow shown in Figure 4. This design flow model is used to create a proposed conversion tool design flow that is shown in Figure 5 below. The conversion tool generates the RTL design files and verifies them using the generated test bench file with user-defined test vectors. All of the test vectors are verified

using OCTAVE. If the results are correct and error falls within the acceptable range, synthesis flow will be the next level of operation. Based on user input parameters, the system will create Verilog HDL code, test bench, and verification results by running a batch file. After generating Verilog HDL RTL code and running the desired number of test vectors, the conversion system needs to compare these test vector results from Design Under Test (DUT) and expected golden values. The conversion tool generates an OCTAVE file to see the error values. The conversion system can generate any number of test vectors based on the computer hardware, such as CPU speed and memory size. The suggested value can be anywhere between 100 and 1,000,000 test vectors. After running the test bench files using Iverilog, the results are compared using OCTAVE file. The OCTAVE-generated test vector comparisons and error plotting are shown in Figure 6 for fixed-to-float and float-to-fixed verifications.

The main code generating floating and fixed point test vectors and test bench files are shown in Figure 7 and Figure 8, respectively. The float-to-fixed data generation shown in Figure 7 starts by setting a random seed for better random value generation. Four levels of precision are used by the data generator. The first quarter of data values are divided by 2048, followed by 256 and 32. The float value generated within this range is then divided by the maximum value of the unsigned integer to get the floating value. The value is then converted to bytes, ultimately getting a binary string.

The fixed-to-float data generator is exactly the same as the previous one. It uses four precision levels, but instead of using the generated float value, the float value is transformed to an integer using 2^(Bits−1).

After reading all the output generated by Icarus Verilog, the code block shown in Figure 9 will read all lines and split them to get input and output values. After that, it will convert the binary to float or fixed using designated functions and also calculate the percent error. The user friendly OCTAVE verification file will be generated as shown in Figure 10. The error plots will be outputted as explained above in Figure 2. The output of the file can be run from MATLAB [19] based on availability.

If the user wants to perform waves-based analysis and verification for certain values, a GTKWave wave window can be used. When the verification code shown in Figure 9 runs and verifies the desired test vectors, it also generates the required vcd file to run in

GTKWave. This will allow the user to verify any test vector possible. This could be useful for reporting as well as golden test vector verification. The generated vcd files for float-to-fixed and fixed-to-float conversion and their GTKWave wave window are shown in Figure 11 and Figure 12, respectively.

3. Implementation and Results

To understand the functionality and effectiveness of the conversion tool, six different blocks are designed, verified and implemented using a Xilinx Virtex 7 FPGA with a 303，600 available Look Up Table (LUT) [20] . The conversion tool is used to generate Verilog HDL design and test bench files, and each design is synthesized and implemented using the Xilinx Vivado design suite. The synthesized schematics of 32-bit fixed-to-float and float-to-fixed point are shown in Figure 13 and Figure 14, respectively.

Generated blocks are implemented and area (LUT), power, temperature, and delay are shown in Table 1. Table 1 shows that implementing 8, 16, and 32-bit fixed-to-float and float-to-fixed requires minimal hardware (less than 0.01%, 0.02%, and 0.05% LUT space) with over 100 MHz clock speed for this FPGA. In addition, design and verification including FPGA implementation of 32-bit fixed-to-float conversion block takes less than three minutes. This created more than 80% time to market (TTM) improvement for block generation.

4. Conclusion

A fixed-to-float and float-to-fixed conversion tool is presented for DSP and communication systems. The design tool generates any size fixed-point number to IEEE floating. This design tool generates fixed-to-floating point (32-bit single precision IEEE 754- 1985) as well as floating-to-fixed point conversion design and verification files using user-friendly GUI. The design tool can be used to generate standalone conversion blocks or part of a larger system design and verification. The functional verification of generated blocks is done during the design process to improve TTM and increase productivity. The conversion tool is designed and can be run using open source tools and can be downloaded from the author’s website [21] . Future work will include 64 -bit floating point numbers and user defined fixed point range.

Acknowledgements

The authors would like to thank Xilinx, Inc. [20] for their valuable support.

Cite this paper

Aslan, S., Mohammad, E. and Salamy, A.H. (2016) Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions. Circuits and Systems, 7, 3874- 3885. http://dx.doi.org/10.4236/cs.2016.711323

References