has been cited by the following article(s):
[1]
|
Advances in Signal Processing and Communication
Lecture Notes in Electrical Engineering,
2019
DOI:10.1007/978-981-13-2553-3_51
|
|
|
[2]
|
LECTOR incorporated differential cascode voltage swing logic (L-DCVSL)
Analog Integrated Circuits and Signal Processing,
2019
DOI:10.1007/s10470-019-01466-2
|
|
|
[3]
|
Revisited Design of Short-pulse Power Gated Approach of Subthreshold Leakage Reduction Technique in Combinational Circuits
2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA),
2018
DOI:10.1109/ICSCAN.2018.8541204
|
|
|
[4]
|
Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design
Journal of Circuits, Systems and Computers,
2018
DOI:10.1142/S0218126619501974
|
|
|
[5]
|
A new low-power 10T SRAM cell with improved read SNM
International Journal of Electronics,
2015
DOI:10.1080/00207217.2014.984642
|
|
|
[6]
|
Analysis and comparison of leakage power reduction techniques in CMOS circuits
2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN),
2015
DOI:10.1109/SPIN.2015.7095351
|
|
|
[7]
|
OIV-CMOS: A novel approach towards leakage power reduction
2015 International Conference on Computer and Computational Sciences (ICCCS),
2015
DOI:10.1109/ICCACS.2015.7361132
|
|
|
[8]
|
POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT
Journal of Circuits, Systems and Computers,
2014
DOI:10.1142/S0218126614501096
|
|
|