A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.org/journal/cs
E-mail: cs@scirp.org

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"A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop"
written by Xinjie Wang, Tadeusz Kwasniewski,
published by Circuits and Systems, Vol.6 No.1, 2015

has been cited by the following article(s):

[1]	A high-resolution time to digital converter design for all digital phase-locked loops
	2021

[2]	Reduction of Power Supply Induced Jitter with Applications to DDR Controllers
	2016

[3]	A reduced reference spur multiplying delay‐locked loop
	International Journal of Circuit Theory and Applications, 2015

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