has been cited by the following article(s):
[1]
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A Machine Learning-Based Post-Route PVT-Aware Power Prediction of Benchmark Circuits at Floorplan Stage of Physical Design
2023 IEEE East-West Design & Test Symposium (EWDTS),
2023
DOI:10.1109/EWDTS59469.2023.10297036
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[2]
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Power Prediction in Register Files Using Machine Learning
IEEE Access,
2022
DOI:10.1109/ACCESS.2022.3172287
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[3]
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Power Prediction in Register Files Using Machine Learning
IEEE Access,
2022
DOI:10.1109/ACCESS.2022.3172287
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[4]
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RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
2021
DOI:10.1109/TCAD.2020.3003276
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