Transient and Permanent Fault Injection in VHDL Description of Digital Circuits ()
1. Introduction
Modern digital systems are typically specified in a high level language such as VHDL. The actual implementation of the system is then performed using this specification. Several important criteria of a system to be designed e.g. testability, power consumption, need to be evaluated. The capability to ascertain the testability of a system at the VHDL level before it is implemented, allows design modifications to achieve the desired goal. A fault injection system provides the capability of introducing a fault at any desired location into the VHDL model of a circuit [1]. The injection technique allows faults to be injected at varying levels of VHDL hierarchy and hence help in evaluating the performance of a testable system.
In general, faults are grouped into two categories: permanent and temporary. Permanent faults that exist in logic circuits are normally identified during offline testing by the manufacturer of ICs, temporary faults on the other hand are of major concern after an IC chip is used in a particular application. Temporary faults can be one of two types: intermittent and transient [2]. Some work has been reported on the development of VHDL model for intermittent faults [3,4], however not much has been reported on transient (soft) fault injection in VHDLbased circuit descriptions [5,6]. The ability to simulate the occurrence of a transient fault in the VHDL description of a circuit is extremely important if the circuit has built-in on-line fault detection capability. In addition the ability to insert permanent faults on single bits or a data word must also be taken into consideration. These features enable the performance of a circuit or a system under faulty conditions to be effectively evaluated before it is implemented.
Fault injection is crucial in an online testable system. It enables a designer to test whether the functional circuit and the checker within the system are operating as specified. Faults in an online testable system are assumed to be mainly single bit faults where a single bit is flipped from a logic 1 to a 0 or vice-versa. They can be both transient and permanent in nature. For (offline) testable systems fault injection helps in evaluating the testability of the entire system before the system is actually implemented. Any internal signal can be accessed at the VHDL level for the purposes of injecting faults, thus ensuring greater controllability and observability of the system.
The fault injection system proposed in this paper will be contained within the instruction VHDL of a system. This maintains the system as platform independent, able to simulate on any VHDL simulation software without extensive knowledge of simulation VHDL, which is a very tedious approach. Delong et al. [7] proposed a technique to accomplish the same goal, offering a different approach to fault injection. Other approaches such as the one offered by Parrotta et al. [8] or the one offered by Vargas et al. [9] involve injection techniques that must be used within simulation VHDL. Other papers approached fault injection differently by using methodologies based on scan paths [10], using outside logic sources to inject faults into VHDL descriptions [11], or by modifying existing circuit architecture [12-14]. Incorporating an injection technique in a VHDL description instead of the simulation code is more easily handled and is portable between design packages. A realistic fault injection system must have the capability to access most signals within a VHDL description including the inputs and outputs of the description; this is crucial for both onand off-line testing.
The organization of the paper is follows. Section 2 discusses the general concept of the proposed fault injection system, and how each of the constituent blocks of the system is implemented in VHDL code. Section 3 illustrates the application of the fault injection system using several examples. Section 4 shows how permanent and transient faults are injected into a system specified in VHDL language. Section 5 is the conclusion.
2. Fault Injection in VHDL Description
A user-friendly fault injection system must evolve from a basic set of specifications. It must allow designers the ability to verify an online testable system, and therefore support injection of transient faults. Furthermore, it needs to have the capability to observe how a circuit behaves in the presence of a fault in an offline testing environment.
The transient fault injection feature proposed in this paper does not just randomly insert faults on its own into the system. It allows predetermination of a rate at which faults are inserted into a data word or data bit; as far as the authors are aware of this feature is not available in any system studied to date. During transient fault injection, random bits in a data word are selected by the system fault insertion. This is a key component of the proposed injection system that enables the designer to simulate faults at more realistic intervals on varying bits in a data word without having to modify the VHDL description every time a fault is inserted in the system. If there is a single input bit or a signal that is directed to the system, a transient fault will always occur on that bit at the interval chosen by the user. This allows the user to focus solely on a single bit when transient fault insertion is desired. If a larger data word is sent to the injection system, it will choose on which bit the fault be injected. This is especially useful in on and offline testing by focusing in on a specific bit or inserting faults randomly across a data word.
The proposed fault injection system is comprised of five blocks with three levels of hierarchy as shown in Figure 1. To invoke the system one component instantiation block is necessary for each data word where faults are to be inserted.
2.1. LFSR Blocks
A major feature of the fault injection system is the ability to insert faults at desired intervals. To accomplish this task the injection system uses pseudo-random sequences. Pseudo-random sequences of maximal length are generated using LFSR’s. The two 16-bit LFSR’s run in parallel constantly generating pseudo-random sequences. Based on the percentage of time that is chosen to insert a fault, a certain number of bits in the two LFSR’s are compared by the fault injection logic block. If that number of bits matches, then a fault is inserted into the system. The data flow through the system that accomplishes this is shown in Figure 2.
Figure 3 presents resulted from a program that was written to simulate two 16-bit LFSR’s running in parallel and certain numbers of bits being matched. A 4-bit control code (Ctrl) which is processed by the Control Logic block determines how many bits need to be matched in the two LFSR’s to control the percentage at which faults are injected. The initial seed to each of the LFSR’s must